Sequential Scan Technique Providing Enhanced Fault Coverage in an Integrated Circuit
AssigneeTexas Instruments Incorporated
InventorDevanathan Varadarajan
Life of this patent
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Abstract
According to an aspect of the present invention, multiple scan enable signals (controlling corresponding scan chains) are used in an integrated circuit, and the scan chains are placed in evaluation mode in non-overlapping durations between scan-in and scan-out operations. In an embodiment, a single clock signal drives the elements in both the scan chains, and the start and end of the non-overlapping durations are timed associated with the edges of the pulses of the clock signal. Multiple pulses of the clock signal may be used between the scan-in and scan-out. According to another aspect of the present invention, the scan elements are conveniently connected to different scan enable signal to take advantage of the non-overlapping durations.
Claims14
A method of testing an integrated circuit using a sequential scan approach, said integrated circuit containing a plurality of scan enable terminals, each of said plurality of scan enable terminals being coupled to a corresponding one of a plurality of sets of scan elements, said plurality of sets of scan elements also being contained in said integrated circuit, each set of scan elements being in a functional mode when the corresponding scan enable terminal is at a first logic value and in a test mode when the corresponding scan enable terminal is at a second logic value, wherein the set of scan elements are connected as a scan chain in said test mode, said method comprising:
- loading each of said scan chains with a corresponding scan vector by placing said plurality of scan enable terminals at said second logic value, wherein said loading is completed by a first time instance;
- scanning out values in each of said scan chains starting from a second time instance;
- and
- providing logical values on said plurality of scan terminals such that a first scan enable terminal is at said first logic value for a first duration and a second scan enable terminal is at said first logic value for a second duration,
- wherein said first duration and said second scan duration are non-overlapping at least for some duration,
- wherein said first scan enable signal and said second scan enable signal are contained in said plurality of scan enable signals, wherein said first duration and said second duration are between said first time instance and said second time instance.
A method of assigning each of a plurality of scan elements among N scan enable lines in a design of an integrated circuit, wherein N represents a positive integer, said method comprising:
- determining a set of controlling elements for each of said plurality of scan elements, wherein a first scan element is a controlling elements for a second scan element if an output of the first scan element affects the input of the second scan element;
- distributing said set of controlling elements among N groups;
- in case a scan element is assigned to a plurality of groups by said distributing, resolving conflict to assign said scan element to one of said plurality of groups according to an approach;
- and
- connecting of each of said N scan enable lines to corresponding one of said N groups.
A computer readable medium carrying one or more sequences of instructions for causing a tester to test an integrated circuit using a sequential scan approach, said integrated circuit containing a plurality of scan enable terminals, each of said plurality of scan enable terminals being coupled to a corresponding one of a plurality of sets of scan elements, said plurality of sets of scan elements also being contained in said integrated circuit, each set of scan elements being in a functional mode when the corresponding scan enable terminal is at a first logic value and in a test mode when the corresponding scan enable terminal is at a second logic value, wherein the set of scan elements are connected as a scan chain in said test mode, wherein execution of said one or more sequences of instructions by one or more processors contained in said tester causes said one or more processors to perform the actions of:
- loading each of said scan chains with a corresponding scan vector by placing said plurality of scan enable terminals at said second logic value, wherein said loading is completed by a first time instance;
- scanning out values in each of said scan chains starting from a second time instance;
- and
- providing logical values on said plurality of scan terminals such that a first scan enable terminal is at said first logic value for a first duration and a second scan enable terminal is at said first logic value for a second duration,
- wherein said first duration and said second scan duration are non-overlapping at least for some duration,
- wherein said first scan enable signal and said second scan enable signal are contained in said plurality of scan enable signals, wherein said first duration and said second duration are between said first time instance and said second time instance.
A computer readable medium carrying one or more sequences of instructions for causing system to provide a design tool which assigns each of a plurality of scan elements among N scan enable lines in a design of an integrated circuit, wherein N represents a positive integer, wherein execution of said one or more sequences of instructions by one or more processors contained in said tester causes said one or more processors to perform the actions of:
- determining a set of controlling elements for each of said plurality of scan elements, wherein a first scan element is a controlling elements for a second scan element if an output of the first scan element affects the input of the second scan element;
- distributing said set of controlling elements among N groups;
- in case a scan element is assigned to a plurality of groups by said distributing, resolving conflict to assign said scan element to one of said plurality of groups according to an approach;
- and
- connecting of each of said N scan enable lines to corresponding one of said N groups.
Dependencies are inferred from the claim text.