Dynamically configurable scan chain testing
OwnerAlessandro Paglieriinventor
Life of this patent
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Abstract
An integrated circuit comprises a circuit under test, a plurality of scan chains coupled to the circuit under test, and a dynamically configurable input selection logic. The dynamically configurable input selection logic couples to the scan chains, receives one or more scan input bit streams, and provides a scan input bit stream to any of the scan chains in accordance with a dynamically controllable control signal. In this manner, pins on the integrated circuit may be shared among multiple scan chains and the integrated circuit may be tested in accordance with any of a plurality of selectable scan chain configurations.
Claims14
An integrated circuit, comprising:
- a circuit under test;
- a plurality of scan chains coupled to the circuit under test;
- and
- a dynamically configurable input selection logic that is coupled to the scan chains, receives one or more scan input bit streams, and provides a scan input bit stream to any of the scan chains in accordance with a dynamically controllable control signal.
An integrated circuit, comprising:
- a circuit under test;
- a plurality of scan chains coupled to the circuit under test;
- and
- means for receiving one or more scan input bit streams and for providing a scan input bit stream to any of the scan chains in accordance with a dynamically controllable control signal.
A method, comprising:
- asserting a control signal to an input selection logic associated with an integrated circuit to cause the input selection logic to provide a common scan input test bit stream to any of a plurality of scan chains dictated by the control signal.
Dependencies are inferred from the claim text.