Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree
AssigneeInternational Business Machines Corporation
InventorsMark Fredrickson, Glen Handlogten, Steven Jones, Chad McBride
Life of this patent
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Abstract
Methods, apparatus, and computer program product are provided for designing logic scan chains for matching gated portions of a clock tree. A clock tree includes a plurality of sections, each section including a gate receiving inputs of a global clock and a chain-specific clock control signal for a particular scan chain. A plurality of scan chains is defined, each including a plurality of latches. Each scan chain latch is connected to a corresponding chain-specific clock tree section.
Claims20
A method for designing logic scan chains for matching gated portions of a clock tree comprising the steps of:
- designing a clock tree including a plurality of sections, each said section including a gate receiving inputs of a global clock and a respective chain-specific clock control signal for a particular scan chain;
- connecting a plurality of latches to a corresponding chain-specific clock tree section to define each respective scan chain of a plurality of scan chains;
- and
- building a scan chain for each of said plurality of latches defining said respective scan chain.
A computer program product for designing logic scan chains for matching gated portions of a clock tree in a computer system, said computer program product including instructions executed by the computer system to cause the computer system to perform the steps of:
- designing a clock tree including a plurality of sections, each said section including a gate receiving inputs of a global clock and a respective chain-specific clock control signal for a particular scan chain;
- connecting a plurality of latches to a corresponding chain-specific clock tree section to define each respective scan chain of a plurality of scan chains;
- and
- building a scan chain for each of said plurality of latches defining said respective scan chain.
Apparatus for designing logic scan chains for matching gated portions of a clock tree comprising the steps of:
- an electronic design program including a logic scan chain design program;
- said logic scan chain design program for designing a clock tree including a plurality of sections, each said section including a gate receiving inputs of a global clock and a respective chain-specific clock control signal for a particular scan chain;
- said logic scan chain design program for connecting a plurality of latches to a corresponding chain-specific clock tree section to define each respective scan chain of a plurality of scan chains;
- and
- said logic scan chain design program for building a scan chain for each of said plurality of latches defining said respective scan chain.
Dependencies are inferred from the claim text.