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US 2007/0168796 A1Published application
On-chip sampling circuit and method
AssigneeMicron Technology, Inc.
InventorsChris Martin, James Johnson, Troy Manning, Brent Keeth
Life of this patent
Estimating the term…
Abstract
Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output pin, or directly to an output pin. In a preferred mode, decode circuits used to select a unique node are serially connected, allowing for a large number of signals to be made available for analyzing without a large impact on circuit layout. Because of the rules related to abstracts, this abstract should not be used in the construction of the claims.
Claims28
A packaged memory device, comprising:
- a plurality of memory cells arranged in an array;
- a plurality of outputs;
- a plurality of peripheral devices for enabling the transmission of data between said outputs and said memory cells;
- a plurality of tap points located throughout said peripheral devices;
- a plurality of serially connected probe circuits, each probe circuit connected to one of said tap points;
- and
- a decode circuit for selecting one of said probe circuits to enable a signal available at a tap point to which said selected probe circuit is connected to be transmitted to one of said outputs.
4 more elements
A packaged memory device, comprising:
- a plurality of memory cells arranged in an array;
- a plurality of outputs;
- a plurality of peripheral devices for enabling the transmission of data between said outputs and said memory cells;
- a plurality of tap points located throughout said peripheral devices;
- a first plurality of serially connected probe circuits, each connected to one of said tap points;
- a first decode circuit for selecting one of said first plurality of probe circuits;
- a second plurality of serially connected probe circuits, each connected to one of said tap points;
- a second decode circuit for selecting one of said second plurality of probe circuits;
- and
- an output select circuit for selecting between said first plurality of probe circuits and said second plurality of probe circuits to enable a signal available at a tap point to which the selected probe circuit is connected to be transmitted to one of said outputs.
7 more elements
A packaged memory device, comprising:
- a plurality of memory cells arranged in an array;
- a plurality of outputs;
- a plurality of peripheral devices for enabling the transmission of data between said outputs and said memory cells;
- a plurality of tap points located throughout said peripheral devices;
- a first plurality of serially connected probe circuits, each connected to one of said tap points,
- a first decode circuit for selecting one of said first plurality of probe circuits to enable a signal available at a tap point to which the selected probe circuit is connected to be transmitted to a first one of said outputs;
- a second plurality of serially connected probe circuits, each connected to one of said tap points;
- a second decode circuit for selecting one of said second plurality of probe circuits;
- a third plurality of serially connected probe circuits, each connected to one of said tap points;
- a third decode circuit for selecting one of said third plurality of probe circuits;
- and
- an output select circuit for selecting between said second plurality of probe circuits and said third plurality of probe circuits to enable a signal available at a tap point to which the selected probe circuit is connected to be transmitted to a second one of said outputs.
9 more elements
A packaged memory device, comprising:
- a plurality of memory cells arranged in an array;
- a plurality of outputs;
- a plurality of peripheral devices for enabling the transmission of data between said outputs and said memory cells;
- a plurality of tap points located throughout said peripheral devices;
- a first plurality of serially connected probe circuits, each connected to one of said tap points;
- a first decode circuit for selecting one of said first plurality of probe circuits;
- a second plurality of serially connected probe circuits, each connected to one of said tap points;
- a first output select circuit for selecting between said first plurality of probe circuits and said second plurality of probe circuits to enable a signal available at a tap point to which the selected probe circuit is connected to be transmitted to a first one of said outputs;
- a third plurality of serially connected probe circuits, each connected to one of said tap points;
- a third decode circuit for selecting one of said third plurality of probe circuits;
- a fourth plurality of serially connected probe circuits, each connected to one of said tap points;
- a fourth decode circuit for selecting one of said fourth plurality of probe circuits;
- and
- a second output select circuit for selecting between said third plurality of probe circuits and said fourth plurality of probe circuits to enable a signal available at a tap point to which the selected probe circuit is connected to be transmitted to a second one of said outputs.
11 more elements
A method of operating a sampling circuit for providing signals from various points within a packaged circuit to be tested, comprising:
- providing a first plurality of signals from nodes within a circuit to be tested to a first plurality of serially connected probe circuits;
- selecting one of said first plurality of probe circuits;
- providing a second plurality of signals from nodes within a circuit to be tested to a second plurality of serially connected probe circuits;
- selecting one of said second plurality of probe circuits;
- and
- selecting one of a signal available at a selected one of said first plurality of probe circuits and a signal available at a selected one of said second plurality of probe circuits to be output.
3 more elements
A method of operating a sampling circuit for providing signals from various points within a packaged circuit to be tested, comprising:
- providing a first plurality of signals from nodes within a circuit to be tested to a first plurality of serially connected probe circuits;
- selecting one of said first plurality of probe circuits to enable a signal available at a node to which the selected probe circuit is connected to be output;
- providing a second plurality of signals from nodes within said circuit to be tested to a second plurality of serially connected probe circuits;
- selecting one of said second plurality of probe circuits;
- providing a third plurality of signals from nodes within said circuit to be tested to a third plurality of serially connected probe circuits;
- selecting one of said third plurality of probe circuits;
- and
- selecting one of a signal available at a selected one of said second plurality of probe circuits and a signal available at a selected one of said third plurality of probe circuits to be output.
5 more elements
A method of operating a sampling circuit for providing signals from various points within a packaged circuit to be tested, comprising:
- providing a first plurality of signals from nodes within a circuit to be tested to a first plurality of serially connected probe circuits;
- selecting one of said first plurality of probe circuits;
- providing a second plurality of signals from nodes within said circuit to be tested to a second plurality of serially connected probe circuits;
- selecting one of a signal available at a selected one of said first plurality of probe circuits and a signal available at a selected one of said second plurality of probe circuits to be output;
- providing a third plurality of signals from nodes within said circuit to be tested to a third plurality of serially connected probe circuits;
- selecting one of said third plurality of probe circuits;
- providing a fourth plurality of signals from nodes within said circuit to be tested to a fourth plurality of serially connected probe circuits;
- selecting one of said fourth plurality of probe circuits;
- and selecting one of a signal available at a selected one of said third plurality of probe circuits and a signal available at a selected one of said fourth plurality of probe circuits to be output.
6 more elements
Dependencies are inferred from the claim text.