Memory with element redundancy
AssigneeMicron Technology, Inc.
InventorFrankie Roohparvar
Life of this patent
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Abstract
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one embodiment of the present invention has primary and redundant elements. A register is used for each redundant element to store the address of a defective primary element and an error code that indicates the type of defect in the defective primary element. Control circuitry is used to control memory operations to the memory array. The control circuitry performs an erase operation algorithm that is specific to an error code when a defective primary element is addressed during an erase operation.
Claims31
A flash memory device comprising:
- a memory array with primary and redundant memory cells;
- and
- redundant register circuitry used to replace the primary memory cells with the redundant memory cells, wherein the redundant register circuitry stores a defect location and an error code indicating a type of defect.
A flash memory device comprising:
- at least one register to store an address of a defective element in a primary memory array,
- the register having at least one data bit to store a defect location and an error code;
- and
- a state machine to execute an algorithm based on the error code stored in the register.
A flash memory device comprising:
- a memory array;
- redundant array elements;
- a register for each redundant array element to store an address of a defective element in the memory array, each register further stores an error code;
- a redundant circuit to redirect address requests from the defective element to an associated redundant array element;
- and
- control circuitry to execute an algorithm based on the error code stored in the register.
A flash memory device comprising:
- a memory array having memory cells arranged in columns and rows;
- at least one redundant row coupled to the memory array to replace an associated defective row in the memory array;
- and
- a register for each redundant row to store the address of the associated defective row, each register further stores an error code, wherein the error code indicates the type of error the redundant row is used to correct.
A flash memory device comprising:
- a memory array having memory cells arranged in columns and rows;
- at least one redundant column mapped to the memory array to replace an associated defective column in the memory array;
- and
- a register for each redundant column to store the address of the associated defective column, each register having at least one extra bit to store an error code, wherein the error code indicates the type of error in the at least one defective column.
A flash memory device comprising:
- a memory array having memory cells arranged in columns and rows;
- at least one redundant row to replace an associated defective row in the memory array;
- a register for each redundant row to store the address of an associated defective row, each register further having at least one bit to store an error code, wherein the error code indicates the type of defect in the associated defective row;
- a redundant circuit to compare address requests to the addresses in the registers, wherein the redundant circuit directs address requests matching addresses in the registers to the associated redundant row instead of the defective row in the memory array;
- and
- control circuitry to execute an erase operation algorithm based on the error code stored in each registers.
A flash memory device comprising:
- a memory array having memory cells arranged in columns and rows;
- at least one redundant row to replace an associated defective row in the memory array;
- at least one redundant column to replace an associated defective column in the memory array;
- and
- a register for each redundant row and each redundant column to store the addresses of associated defective rows and columns, each register having at least one bit to store an error code, wherein the error code indicates the type of defect the redundant row or column is used to correct.
Dependencies are inferred from the claim text.