Circuit and method for testing embedded phase-locked loop circuit

A method for testing an embedded phase-locked loop (PLL) circuit comprising steps of:

• providing a first clock signal to an embedded phase-locked loop (PLL) circuit to be tested;
• generating a PLL clock signal of a first frequency by said embedded PLL in response to said first clock signal;
• sampling said PLL clock signal of said first frequency with a second clock signal of a second frequency to generate a first sampled signal, wherein said second frequency is different from said first frequency but has a first correlation with said first frequency;
• sampling said first sampled signal with said second clock signal of said second frequency to generate a second sampled signal;
• logically operating said first sampled signal and said second sampled signal to obtain a logic operational result;
• and
• directly referring to said logic operational result to determine whether said embedded PLL circuit is in a normal operation condition.

A method for testing an embedded phase-locked loop (PLL) circuit comprising steps of:

• providing a first clock signal to an embedded phase-locked loop (PLL) circuit to be tested;
• generating a PLL clock signal of a first frequency by said embedded PLL in response to said first clock signal;
• sampling said PLL clock signal of said first frequency with a second clock signal of a second frequency to generate a first sampled signal, wherein said second frequency is different from said first frequency but has a first correlation with said first frequency;
• sampling said first sampled signal with said second clock signal of said second frequency to generate a second sampled signal;
• inverting said second clock signal of said second frequency to obtain an inverted second clock signal;
• sampling said PLL clock signal of said first frequency with said inverted second clock signal to generate a third sampled signal;
• sampling said third sampled signal with said inverted second clock signal to generate a fourth sampled signal;
• logically operating said first sampled signal and said second sampled signal to obtain a first logic operational output;
• logically operating said third sampled signal and said fourth sampled signal to obtain a second logic operational output;
• and
• logically operating said first logic operational output and said second logic operational output to obtain an indication signal;
• and
• directly referring to said indication signal to determine whether said embedded PLL circuit is in a normal operation condition.