Apparatus and method for reducing test resources in testing drams
OwnerChris Cooper, Siang Giam +4inventors
InventorsChris Cooper, Siang Giam, Jerry McBride, Scott Gatzemeier, Scott Ayres, David Brown
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Abstract
An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.
Claims21
(canceled)
A wafer probe for testing a memory device, the wafer probe comprising:
- a plurality of conductive pins having a control pin configured to output to at least one memory device a control signal having a precharge signal defined by a first portion of the control signal and a latch signal defined by a second portion of the control signal.
Control circuitry for use with a wafer probe in testing a computer memory device, the control circuitry comprising:
- a first input configured to receive from a control pin of a wafer probe a control signal having a precharge signal defined by a first portion of the control signal and a latch signal defined by a second portion of the control signal.
A device for testing a computer memory device, the testing device comprising;
- clock circuitry configured to output a control signal having a precharge signal defined by a first portion of the control signal and a latch signal defined by a second portion of the control signal;
- and
- a plurality of conductive pins, the plurality of conductive pins having a control pin coupled to the clock circuitry and configured to output the control signal to at least one memory device.
Dependencies are inferred from the claim text.