Detector in parallel with a logic component
AssigneeIntel Corporation
InventorItay Admon
Life of this patent
Estimating the term…
Abstract
One or more detectors are provided for processing input in parallel with a logic component receiving the same input. Apparatus described herein include one or more logic components that are configured to perform logical operations on an input vector, and one or more detectors that are configured to receive a portion of the input vector. The detector is further configured to perform detections on this portion of the input vector in parallel with the logical operation. Methods described herein include identifying a portion of the input vector, wherein the portion of the input vector appears an output of the logic component, and analyzing the portion of the vector in parallel with a logical operation performed by the logic component.
Claims30
Apparatus comprising:
- at least a logic component configured to perform at least one logical operation on an input vector;
- and
- a detector configured to receive as input at least a portion of the input vector and to perform at least one detection on the portion of the input vector in parallel with the logical operation.
A method comprising:
- identifying a portion of a vector input to a logic component, wherein the portion of the vector appears in an output of the logic component;
- and
- analyzing the portion of the vector in parallel with a logic operation performed by the logic component.
One or more computer readable media comprising computer executable instructions that, when executed, direct a computing device to:
- identify a portion of a vector input to a logic component, wherein the portion of the vector is to be included in an output of the logic component;
- and
- analyze the portion of the vector in parallel with a logic operation to be performed by the logic component.
A system comprising:
- at least one codec;
- a circuit coupled to receive input from the codec and including:
- at least a logic component configured to perform at least one logical operation on an input vector received from the codec and to generate an output vector resulting from performing the logical operation on the input vector;
- and
- a detector configured to receive as input at least a portion of the input vector and to perform at least one detection on the portion of the input vector in parallel with the logical operation and to generate a detection signal representing the detection.
Dependencies are inferred from the claim text.