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AssigneePegre Semiconductors, LLC
InventorKatsuki Hazama
Estimating the term…
A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the first bits and a bit of the N-order of the second bits are stored in one of the cells, the N being an integral number. A voltage corresponding to the N-order bits is generated and applied to the one of the cells in response to an address information corresponding thereto. Another semiconductor device has multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by n (n≧2) number of bits (X1, X2, . . . , Xn). A logical address is converted into a physical address of the physical address space. Judging is made whether a logical address space including the logical address matches the physical address space. When matched, the most significant bit X1 is specified once using a reference value. The specified bit is output from one of the cells corresponding to the physical address. If not matched, the bits (X2, . . . , Xn) are specified by n-time specifying operation maximum using maximum n number of different reference values. The data writing/reading operations to/from the semiconductor devices can be stored in a computer readable medium as program codes for causing a computer to execute these operations.
A semiconductor device comprising:
A method of writing data of bits in a semiconductor device having a plurality of multilevel memory cells, each cell storing at least three levels of data each, comprising the steps of:
A computer readable medium storing program code for causing a computer to write data of bits in a semiconductor device having a plurality of multilevel memory cells, each cell storing at least three levels of-data each, comprising:
A semiconductor device comprising:
A method of reading n (n≧2) number of bits (X1, X2, . . . , Xn) from a plurality of multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by the bits (X1, X2, . . . , Xn), comprising the steps of:
A method of reading n (n≧2) number of bits (X1, X2, . . . , Xn) from a plurality of multilevel memory cells arranged so as to correspond to a physical address space, each cell having at least one transistor, each cell storing 2n levels of data each expressed by the bits (X1, X2, . . . , and Xn), comprising the steps of:
A method of reading n (n≧2) number of bits (X1, X2, . . . , Xn) from a plurality of multilevel memory cells arranged so as to correspond to a physical address space, each cell having at least one transistor, each cell storing 2n levels of data each expressed by the bits (X1, X2, . . . , and Xn), comprising the steps of:
A computer readable medium storing program code for causing a computer to read n (n≧2) number of bits (X1, X2, . . . , Xn) from a plurality of multilevel memory cells arranged so as to correspond to a physical address space, each cell storing 2n levels of data each expressed by the bits (X1, X2, . . . , Xn), comprising:
A computer readable medium storing program code for causing a computer to read n (n≧2) number of bits (X1, X2, . . . , Xn) from a plurality of multilevel memory cells arranged so as to correspond to a physical address space, each cell having at least one transistor, each cell storing 2n levels of data each expressed by the bits (X1, X2, . . . , Xn), comprising:
A computer readable medium storing program code for causing a computer to read n (n≧2) number of bits (X1, X2, . . . , Xn) from a plurality of multilevel memory cells arranged so as to correspond to a physical address space, each cell having at least one transistor, each cell storing 2n levels of data each expressed by the bits (X1, X2, . . . , Xn), comprising:
A semiconductor device having a plurality of multilevel memory cells, each cell storing one of at least three levels of data each, the semiconductor device comprising a bit disperser for dispersing bits over the plurality of multilevel memory cells to store the bits therein, the bits constituting at least one code data coded by a coding method to be stored in the cells.
A computer readable medium storing program code for causing a computer to store data in a semiconductor device having a plurality of multilevel memory cells, each cell storing one of at least three levels of data each, comprising a program code means for dispersing bits over the plurality of multilevel memory cells to store the bits therein, the bits constituting at least one code data coded by a coding method to be stored in the cells.
A method of writing at least one code data coded by a coding method in a semiconductor device having a plurality of multilevel memory cells, each cell storing one of at least three levels of data each, the method comprising the step of dispersing bits constituting the code data over the plurality of multilevel memory cells.
A computer readable medium storing program code for causing a computer to write at least one code data coded by a coding method in a semiconductor device having a plurality of multilevel memory cells, each cell storing one of at least three levels of data each, comprising the program code for dispersing bits constituting the code data over the plurality of multilevel memory cells.
A semiconductor device comprising:
A method of reading data stored in a semiconductor device having at least one multilevel memory cell provided so as to correspond to a physical addresses converted from an input logical address, the cell having a control gate, a source and a drain, the cell storing at least three levels of data each, the data being expressed by data components of two-dimension or more;
A computer readable medium storing program code for causing a computer to read data stored in a semiconductor device having at least one multilevel memory cell provided so as to correspond to a physical addresses converted from an input logical address, the cell having a control gate, a source and a drain, the cell storing at least three levels of data each, the data being expressed by data components of two-dimension or more;
A semiconductor device comprising:
A semiconductor device comprising:
Dependencies are inferred from the claim text.