US 2007/0168781 A1 · Fully-buffered dual in-line memory module with fault correction

Abstract

A memory module comprises first memory that stores data in memory blocks; second memory that temporarily stores data from at least one of the memory blocks and third memory for storing a relationship between addresses of the at least one of the memory blocks in the first memory and corresponding addresses of the data from the at least one of the memory blocks in the second memory. Storage capacities of the second and third memories are less than a storage capacity of the first memory. A control module selectively transfers data in the at least one of the memory blocks in the first memory to the second memory and stores and retrieves data from the second memory for the at least one of the memory blocks based on the relationship during the testing.

Claims43

Dependent claims

A memory module comprising:

first memory that stores data in memory blocks;
second memory that temporarily stores data from at least one of said memory blocks;
third memory for storing a relationship between addresses of said at least one of said memory blocks in said first memory and corresponding addresses of said data from said at least one of said memory blocks in said second memory, wherein storage capacities of said second and third memories are less than a storage capacity of said first memory;
and
a control module that selectively transfers data in said at least one of said memory blocks in said first memory to said second memory and that stores and retrieves data from said second memory for said at least one of said memory blocks based on said relationship during said testing of said at least one of said memory blocks.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/584,946Filed 23 Oct 2006

Priority

30 May 2002

Published

19 Jul 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification22 codes

G06F 11/1064
In individual solid state devices: in cache or content addressable memories
G06F 11/1008
Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's: in individual solid state devices
G11C 11/406
Forming cells needing refreshing or charge regeneration, i.e. dynamic cells: management or control of the refreshing or charge-regeneration cycles
G11C 29/02
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: detection or location of defective…

Family

Application60/384,371Us provisional application · filed 30 May 2002

Application10/184,334Division · filed 26 Jun 2002

Application11/328,373Continuation · filed 9 Jan 2006

Application11/328,373Division · filed 9 Jan 2006

Application60/821,442Us provisional application · filed 4 Aug 2006

Application60/823,989Us provisional application · filed 30 Aug 2006

Application60/825,361Us provisional application · filed 12 Sep 2006

Application60/827,976Us provisional application · filed 3 Oct 2006

Application11/584,946Continuation · filed 23 Oct 2006

US 7,073,099 B1Related patent

US 7,818,639 B2Related patent

US 7,962,809 B1Related patent

US 2007/0168781 A1This patent

From the US filing history. Foreign family members aren’t listed.

Fully-buffered dual in-line memory module with fault correction

Life of this patent

Fully-buffered dual in-line memory module with fault correction

Life of this patent

Abstract

Claims43