Testing of a CAM

A system for testing a memory device comprising:

• a processor;
• and
• the memory device coupled to the processor;
• the memory device having at least one memory storage location, the processor loading the memory storage location with a predetermined code, the predetermined code including a plurality of data segments, each data segment containing Gray code data which differs from Gray code data of an adjacent data segment by one data bit;
• and
• a testing component within the processor for comparing the Gray code data of each data segment with a first comparison Gray code pattern and a second comparison code pattern stored in a comparison register for an expected result, the second comparison code pattern differing from the first comparison Gray code pattern by one bit.

A system for testing a memory device comprising:

• a plurality of circuits, each circuit configured to provide a segment of a Gray code pattern;
• wherein each circuit comprises a plurality of gates;
• at least one memory storage location configured to store a predetermined code, the predetermined code including a plurality of data segments, each data segment containing a Gray code which differs from an adjacent data segment by one data bit;
• a first gate of the plurality of gates configured to test a first bit of each data segment of at least one memory storage location by comparing the first data bit of each data segment of the at least one memory storage location with a first comparison Gray code pattern and a second comparison code pattern stored in a comparison register for an expected result, the second comparison code pattern differing from the first comparison Gray code pattern by one bit;
• and
• a second gate configured to identify and output an error indication if the expected result is not obtained.

A system for testing a memory device comprising:

• a processor;
• and
• the memory device coupled to the processor;
• the memory device having at least one memory storage location, the processor configured to load the memory storage location with a predetermined code, the predetermined code including a plurality of data segment, each data segment containing Gray code data;
• and
• a testing component within the processor for comparing the Gray code data of each data segment with a first comparison Gray code pattern and a second comparison code pattern stored in a comparison register for an expected result, the second comparison code pattern differing from the first comparison Gray code pattern by one bit.