Error detection and correction in a CAM
AssigneeMicron Technology, Inc.
InventorsAlon Regev, Zvi Regev
Life of this patent
Estimating the term…
Abstract
An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of the CAM locations that it is connected to in sequence. If an error is detected, the error detection and correction circuit rewrites the CAM location with the correct data. Multiple error correction and detection circuits can be used in the CAM device to test multiple CAM locations simultaneously.
Claims20
1-59. (canceled)
An memory device integrated circuit, comprising:
- a plurality of banks of content addressable memory cells, and
- a plurality of refresh and error detection and correction circuits, each refresh and error detection and correction circuit being associated with and connected to a respective bank, each refresh and error detection and correction circuit being adapted to test memory cells in its associated bank for errors, detect errors within the cells and correct any detected errors during a refresh operation of the integrated circuit,
- wherein each refresh and error detection and correction circuit is adapted to correct multiple-bit errors in a memory cell detected as having a multiple-bit error.
A memory device integrated circuit comprising:
- a bank of memory cells;
- an address generator adapted to generate a test address for a memory cell to be tested, the address generator being connected to the bank;
- a state machine connected to the address generator and being adapted to output a signal to the address generator when it is time to generate the test address, the state machine being further adapted to provide access signals to the bank when it is time to access the memory cell to be tested;
- and
- a test circuit connected to the bank, the test circuit adapted to input a content of the memory cell to be tested, determine whether the input content contains a multiple-bit error, and correct the multiple-bit error if it is determined that the input content contains the error.
A method of performing error detection and correction in a content addressable memory, the method comprising:
- generating test addresses for memory cells to be tested in a plurality of banks of memory cells;
- inputting content of each memory cell being tested;
- determining whether any of the input content contains errors by evaluating additional memory bits associated with each memory cell being tested to determine if any of the cells has an error;
- correcting any errors if it is determined that the input content contains errors;
- and
- repeating the generating step through the correcting step such that all memory cells in all banks of the content addressable memory are tested.
Dependencies are inferred from the claim text.