US 2007/0168773 A1Published application

Semiconductor memory unit with repair circuit

AssigneeRenesas Technology Corp.

InventorAtsushi Miyanishi

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Abstract

A semiconductor memory unit with a repair circuit includes a controller, a 2-to-1 selector, an address decoder and an address comparator. The controller supplies the 2-to-1 selector and the address comparator with a setup signal to carry out the following control. When the 2-to-1 selector is controlled to supply the address decoder with a repair address signal, the address comparator is controlled to have a repair signal information holding section, which is installed in the address comparator, hold the repair address decoded by the address decoder. When the 2-to-1 selector is controlled to supply the address decoder with a read/write address signal, the address comparator is controlled to compare the read/write address with the repair address. The semiconductor memory unit can obviate the need for a repair address decoder, thereby reducing the unit area.

Claims1

Dependent claims

A semiconductor memory unit with a repair circuit that compares a read/write target memory address with a repair target memory address, and activates, when the two addresses agree with each other, a corresponding repair memory instead of a corresponding read/write target memory, said semiconductor memory unit with the repair circuit comprising:

an address memory for storing the repair target memory address;
a shared address decoder for decoding a read/write target memory address signal supplied from outside, and a repair target memory address signal output from said repair address memory;
a selector for selecting one of the read/write target memory address signal and the repair target memory address signal to be supplied to said shared address decoder;
and
an address comparator that includes a repair signal information holding section for holding the repair target memory address decoded by said shared address decoder, and compares the repair target memory address with the read/write target memory address decoded by said shared address decoder.

2 more elements

Dependencies are inferred from the claim text.