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US 2007/0168772 A1Published application
Circuits and methods for repairing defects in memory devices
AssigneeMicron Technology, Inc.
InventorKenneth Marr
Life of this patent
Estimating the term…
Abstract
Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The supply control circuit isolates a selected memory segment from the supply source when the selected memory segment is defective. The memory device replaces a defective memory segment with a redundant segment. Other embodiments are described and claimed.
Claims47
A device comprising:
- a plurality of supply paths coupled to a supply node;
- a plurality of memory segments, each of the memory segments being coupled to the supply node via one of the supply paths;
- a plurality of switching units, each of the switching units being coupled to one of the supply paths and to a corresponding memory segment, the corresponding memory segment being one of the memory segments;
- wherein each of the switching units includes an enable mode for coupling the corresponding memory segment to the supply node, and a disable mode for decoupling the corresponding memory segment from the supply node;
- and
- at least one redundant segment for replacing at least one memory segment of the plurality of memory segments.
3 more elements
A device comprising:
- a first supply node and a second supply node;
- a plurality of switching units, each of the switching units being coupled to the first supply node;
- and
- a plurality of memory segments, each of the memory segments being coupled to the first supply node through one of the switching units and including a resistance between an internal node and the second supply node, wherein the internal node coupling to one memory segment is different from the internal node coupling to another memory segment, wherein the resistance of at least one memory segment equals a first resistance.
1 more element
A device comprising:
- a memory cell including a first storage node and a second storage node and including:
- a latch coupled to the first and second storage nodes and to an internal node;
- a first access element for accessing the first storage node;
- and
- a second access element for accessing the second storage node;
- and
- a switching unit coupled between the internal node and a supply node.
4 more elements
A device comprising:
- a plurality of memory cells, at least one of the memory cells being coupled between a first internal node and a second internal node and including:
- a first storage node and a second storage node;
- a latch coupled to the first and second storage nodes and coupled between the first and second internal nodes;
- a first access element for accessing the first storage node;
- and
- a second access element for accessing the second storage node;
- a first switching unit coupled between the first internal node and a first supply node;
- and
- a second switching unit coupled between the second internal node and a second supply node.
6 more elements
A device comprising:
- a first supply node and a second supply node;
- a plurality of memory segments, each of the memory segments being coupled between the first supply node and an internal node, each of the memory segments including a plurality of memory cells, each of the memory cells including:
- a first storage node and a second storage node;
- a latch coupled to the first and second storage node and coupled in between the first supply node and the internal node;
- a first access element for accessing the first storage node;
- and
- a second access element for accessing the second storage node;
- and
- a plurality of switching units, each of the switching units being coupled between one of the memory segments and the second supply node.
6 more elements
A system comprising:
- 2a processor;
- and
- a static random access memory device coupled to the processor, the static random access memory device including:
- a plurality of supply paths coupled to a supply node;
- a plurality of memory segments, each of the memory segments being coupled to the supply node via one of the supply paths;
- a plurality of switching units, each of the switching units being coupled to one of the supply paths and to a corresponding memory segment, the corresponding memory segment being one of the memory segments;
- wherein each of the switching units includes an enable mode for coupling the corresponding memory segment to the supply node, and a disable mode for decoupling the corresponding memory segment from the supply node;
- and
- at least one redundant segment for replacing at least one memory segment of the plurality of memory segments.
6 more elements
A method comprising:
- determining a condition of a plurality of memory segments;
- storing an address of a selected memory segment among the memory segments when the selected memory segment is defective;
- isolating the selected memory segment from a supply source when the selected memory segment is defective;
- and
- replacing the selected memory segment with a redundant segment when the selected memory segment is defective.
2 more elements
A method comprising:
- testing a plurality of memory segments in which at least one of the memory segments at an unknown address is defective;
- identifying an address of a defective memory segment of the plurality of memory segments;
- storing the address as stored address;
- isolating the defective memory segment from a voltage source based on the stored address;
- and
- replacing the defective memory segment with a redundant segment based on the stored address.
3 more elements
Dependencies are inferred from the claim text.