Circuits and methods for repairing defects in memory devices

A device comprising:

• a first supply node and a second supply node;
• a supply control circuit coupled between the first supply node and a plurality of internal nodes;
• a plurality of memory segments, each of the memory segments being coupled between one of the internal nodes and the second supply node;
• and
• at least one redundant segment coupled to the memory segments for maintaining a storage capacity of device.

A system comprising:

• a processor;
• and
• a static random access memory device coupled to the processor, the static random access memory device including:
• a supply node for providing a supply source;
• a memory array having multiple memory segments, each of the memory segment being coupled to the supply node via a supply path for receiving the supply source;
• a supply control circuit for isolating a selected memory segment of the multiple memory segments from the supply node when the selected memory segment is defective;
• and
• a redundant array for replacing the selected memory segment when the selected memory segment is defective.

A method comprising:

• placing a first switch between a first memory segment and a supply node;
• placing a second switch between a second memory segment and the supply node;
• and
• disabling the first switch to prevent the first memory segment from receiving a supply source at the supply node.

A method comprising:

• receiving an input address;
• comparing the input address with a stored address;
• accessing a memory segment in a memory array when the input address and the stored address are mismatched;
• and
• accessing a memory segment in a redundant array when the input address and the stored address are matched, wherein the memory array includes a memory segment having circuit short to a supply node.