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US 2007/0168768 A1Published application
ECC coding for high speed implementation
AssigneeIntel Corporation
InventorsDuane Galbi, Ranjit Loboprabhu, Jose Niell
Life of this patent
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Abstract
Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.
Claims20
A method, comprising:
- performing a parity check for first and second subsets of bits in an instruction word, the first and second subsets collectively covering all of the bits in the instruction word;
- and
- detecting if a single error is present in the instruction word based on the parity checks for the first and second subsets of bits.
An integrated circuit, comprising:
- logic to implement an error correction code (ECC) mechanism employing a plurality of subsets of bits, each subset of bits comprising a unique set of bit positions for an instruction word;
- logic to perform a parity check for first and second subsets of bits in the plurality of subsets of bits, the first and second subsets collectively covering all of the bits in the instruction word;
- and
- logic to detect if a single error is present in the instruction word based on the parity checks for the first and second subsets of bits.
1 more element
A network line card, comprising:
- a printed circuit board (PCB);
- a backplane connector, coupled to the PCB;
- an interconnect comprising a plurality of address and data bus lines formed in the PCB;
- Rambus Dynamic Random Access Memory (RDRAM), coupled to the interconnect;
- and
- a network processor unit, coupled to the interconnect, including a plurality of compute engines, at least one compute engine including,
- a control store to store instruction words;
- an instruction register coupled to the control store;
- an execution datapath;
- logic to implement an error correction code (ECC) mechanism employing a plurality of subsets of bits, each subset of bits comprising a unique set of bit positions for the instruction register;
- logic to perform a parity check for first and second subsets of bits in the plurality of subsets of bits, the first and second subsets collectively covering all of the bits in the instruction word;
- and
- logic to detect if a single error is present in an instruction word based on the parity checks for the first and second subsets of bits.
10 more elements
Dependencies are inferred from the claim text.