Method and apparatus for dumping a process memory space
AssigneeTelefonaktiebolaget LM Ericsson (publ)
InventorsOla Nilsson, Staffan Mansson
Life of this patent
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Abstract
A method and apparatus for facilitating postmortem debugging of a computer hardware failure. When an error occurs, a controller places a memory, such as a synchronous dynamic random access memory (SDRAM), in a self refresh mode in which the memory is able to retain its data contents. The data contents of the SDRAM are then written to a secondary storage location and a hardware reset is performed.
Claims25
A method of facilitating post-mortem debugging of a computer, comprising:
- detecting an error event by the computer;
- saving, by the computer, register contents into a memory;
- placing, by the computer, the memory into self refresh mode;
- and
- reading, by the computer, the data contents of the memory to a secondary storage location.
A method of facilitating the analysis of a computer failure, comprising:
- placing the computer into a known hardware state;
- saving the memory contents to a secondary storage location;
- and
- dumping memory contents during a memory self refresh.
A method for automatically restarting a computer system in the event of a software failure, comprising:
- placing, by a watchdog hardware circuit, memory in self refresh, and
- resetting the system.
A method of controlled error handling in a computer, comprising:
- detecting, by the computer, an error event;
- calling, by the operating system of the computer, error handling code;
- saving, by the error handling code, contents of registers into random access memory (RAM);
- placing, by the operating system, the RAM into self refresh mode;
- and
- resetting the computer hardware.
A method for automatically restarting computer hardware in the event of a software failure, comprising:
- detecting, by a watchdog reset circuit, a software failure;
- placing, by a synchronous dynamic random access memory (SDRAM) controller, SDRAM in self refresh mode;
- and
- resetting the computer hardware.
An apparatus adapted to facilitate post-mortem debugging of a computer platform, comprising:
- at least one memory cell;
- a memory interface coupled to the at least one memory cell
- a watchdog circuit adapted to place the at least one memory cell in self refresh mode;
- a central processing unit (CPU) having at least one register and being adapted to read, transfer and operate upon contents between the at least one register and the at least one memory cell via the memory interface;
- and
- at least one bus coupling the at least one memory cell, the memory interface, the CPU and the watchdog circuit.
An apparatus for automatically restarting a computer system in the event of a software failure, comprising:
- at least one memory cell:
- a watchdog hardware circuit adapted to detect a software failure;
- a microprocessor having at least one register, the microprocessor being adapted to:
- place the at least one memory cell in self refresh mode in the event of the detection of a software failure;
- and
- reset the computer system;
- and
- at least one bus coupling the at least one memory cell, the watchdog hardware circuit and the microprocessor.
Dependencies are inferred from the claim text.