Failsoft system for multiple CPU system
AssigneeSilicon Graphics, Inc.
InventorsPatrick Donlin, Samuel Watters
Life of this patent
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Abstract
A cpu-set type multiprocessor system allows a cpu of a cpu-set that has a hardware exception to disable itself and notify the system. The system assigns processes of the cpu-set that include the problem cpu to another cpu-set. The disabling of the problem cpu and transfer of the related processes to another cpu-set allows the system to failsoft so that other cpu-sets the multiprocessor system can continue to run and a recovery of the processes being run on the problem cpu-set occurs.
Claims12
A method, comprising:
- determining whether a first processor of a first set of processors in a multiprocessor system has encountered a problem;
- and
- deactivating the first set of processors.
A method, comprising:
- determining whether a first processor of a first set of processors in a multiprocessor system has encountered a hardware exception;
- deactivating the first set of processors, comprising idling and disabling the first processor;
- sending an alert concerning the first processor;
- transferring processes from the first processor of the first set to a first processor of a second set of processors;
- and
- transferring processes of other processors of the first set to processors of the second set;
- and
- assigning the processors of the first set other than the first processor to a global processor set for reassignment to other processes;
- and
- continuing processing by other processor sets of the multiprocessor system not in the first set.
A system, comprising:
- a multiprocessor system, comprising:
- a control processor;
- and
- processors divided into sets where a processor of a first set that has a problem disables itself and sends a message to the control processor and the control processor transfers processes of the first set to processors of a second set.
A system, comprising:
- multiprocessors divided into sets;
- means for detecting a processor of a set having a problem;
- and
- means for transferring processes of the set to another set.
A computer readable storage for controlling a computer having a process determining whether a first processor of a first set of processors in a multiprocessor system has encountered a problem and deactivating the first set of processors.
A computer readable storage for controlling a computer having a data failsoft structure comprising an entry for each processor of a multiprocessor system divided into sets of processors, each entry comprising a status code indicating whether the processor is disable, enabled or having a problem and a pointer indicating threads of eth processor having the problem.
A computer readable storage for controlling a computer having a processor set reassignment data structure for a multiprocessor system divided into sets of processors, the data structure comprising a first processor set identifier identifying a first set of processors including a processor having a problem, a processor identifier identifying a processor of the set having the problem and a second processor identifier identifying a second set of processors to handle the processes of the first set.
Dependencies are inferred from the claim text.