MCU with low power mode of operation
AssigneeSilicon Laboratories Inc.
InventorKa Leung
Life of this patent
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Abstract
A low power system is disclosed for working in conjunction with a digital circuit that is disposed between positive and negative terminals. The system includes an internal voltage generator for increasing, for at least a first portion of the digital circuit, a voltage difference between the at least a first portion of the digital circuit and the voltage on at least one of the positive and negative terminals during a low power mode of operation. This allows the voltage across the at least first portion of the digital circuit to be less than the full voltage across the positive and negative terminals.
Claims28
A low power system for working in conjunction with a digital circuit that is disposed between positive and negative terminals, comprising:
- an internal voltage generator for increasing, for at least a first portion of the digital circuit, a voltage difference between the at least a first portion of the digital circuit and the voltage on at least one of the positive and negative terminals during a low power mode of operation, such that the voltage across said at least first portion of the digital circuit is less than the full voltage across the positive and negative terminals.
A processing system with a suspend mode of operation to allow low power operation, the processing system operable to receive power across positive and negative terminals, comprising:
- an instruction based digital processing block;
- a clock section for generating a system clock for clocking said digital processing block;
- an internal voltage generator for decreasing the voltage across the digital processing block in a suspend mode of operation;
- and
- a mode controller for controlling said internal voltage generator to operate in a full power mode of operation wherein the power across said digital processing block is substantially equal to the voltage across the positive and negative terminals, and in the suspend mode of operation to reduce the voltage across said digital processing block to less than voltage across the positive and negative terminals.
A method for operating a digital circuit portion of an integrated circuit, which integrated circuit is disposed between positive and negative terminals, in a low power mode of operation, comprising the steps of:
- disposing an internal voltage generator between an intermediate node within the integrated circuit and one of the positive and negative terminals, wherein at least a first portion of the digital circuit is disposed between the intermediate node and the other of the positive and negative terminals;
- and
- increasing the voltage of the internal voltage generator to thus increase the voltage difference between the intermediate node and the one of the positive and negative terminals during a low power mode of operation, such that the voltage across the at least first portion of the digital circuit is less than the fill voltage across the positive and negative terminals.
A method for operating a processing system in a a suspend mode of operation to allow low power operation, the processing system operable to receive power across positive and negative terminals, comprising the steps of:
- executing instructions with an instruction based digital processing block;
- generating a system clock with a clock section for clocking the digital processing block;
- decreasing the voltage across the digital processing block in a suspend mode of operation with an internal voltage generator;
- and
- controlling the internal voltage generator with a mode controller to operate in a full power mode of operation wherein the power across the digital processing block is substantially equal to the voltage across the positive and negative terminals, and in the suspend mode of operation to reduce the voltage across the digital processing block to less than voltage across the positive and negative terminals.
Dependencies are inferred from the claim text.