System and method for acceleration of streams of dependent instructions within a microprocessor
AssigneeBroadcom Corporation
InventorsSophie Mary Wilson, Alexander James Burr
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Abstract
A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is implemented within a larger general purpose processor for handling the streams of dependent instructions.
Claims18
A method for processing instructions in an integrated circuit (IC) chip comprising a processor and a sequential accelerator, the method comprising:
- storing one or more operations to be processed by the sequential accelerator;
- receiving and processing a first instruction in the processor;
- and
- responsive to the processing of the first instruction by the processor:
- processing the one or more operations in the sequential accelerator, and
- providing the results of the one or more operations in the sequential accelerator to the processor.
An integrated circuit for processing sequential instructions, the IC comprising:
- a processor;
- and
- a sequential accelerator;
- wherein the processor is configured to transfer to the sequential accelerator one or more operations to be processed by the sequential accelerator when the processor executes an instruction triggering processing by the sequential accelerator of the one or more operations.
A pipeline located within a processor, the pipeline comprising:
- an instruction decode stage;
- and
- an instruction configuration path, the instruction configuration path for configuring a sequential accelerator to process an operation;
- wherein if the instruction decode stage receives an instruction requesting the configuration of the sequential accelerator to process the operation, the instruction decode stage decodes the instruction to determine the operation to be processed by the sequential accelerator and triggers the configuration of the sequential accelerator, using the instruction configuration path, to enable it to process the operation.
Dependencies are inferred from the claim text.