Methods and arrangements for conditional execution of instructions in parallel processing environment

A very long instruction word (VLIW) processing apparatus comprising:

• a memory to store VLIWs;
• a decoder to separate the VLIWs into processable sequences, some of the processable sequences having a condition;
• a first processing unit coupled to the decoder;
• and
• at least a second processing unit coupled to the decoder, where the first processing unit and the at least a second processing unit each execute processable sequences independently of each other in response to no conditions in the processable sequences and the first processing unit and the at least second processing unit are logically coupled in response to a condition in the processable sequence.

A computer program product comprising a computer useable medium having a computer readable program, wherein the computer readable program when executed on a computer causes the computer to:

• load a VLIW from at least one memory unit into an instruction word decoder;
• separate the VLIW into processable sequences, each processable sequence processable by a processing unit from a plurality of processing units, where in the absence of a condition in processable sequence the processing units will process the processable sequences independently;
• and
• couple a processing unit to another processing unit for at least one clock cycle to facilitate processing of a processable sequence with a condition.