Memory array programming circuit and a method for using the circuit
AssigneeSaifun Semiconductors Ltd.
InventorsYan Polansky, Avi Lavan
Life of this patent
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Abstract
A multi-level cell (MLC) memory array may be programmed using a programming circuit having a binary input register to store data to be input into the MLC array and a register to store a programming vector, where each element in the programming vector corresponds to a charge storage region of an MLC in the array. A controller may map pairs of bits from the input register to elements in the programming vector, such that mapping a pair of bits to an element of the programming vector may set the vector element to a “program” value if the pair of bits corresponds to at least one specific program state associated with the programming vector.
Claims38
A method of programming a multi-level cell (MLC) memory array comprising deriving a programming vector associated with at least one specific program state.
A method of programming a set of multi-level cells comprising:
- Concurrently applying programming pulses to at least two cells in said set of multi-level cells, which at least two cells are designated for programming to different threshold voltages corresponding to at least two specific program states.
A method of programming a multi-level cell (MLC) memory array comprising:
- deriving at least one programming vector associated with at least two specific program states, and concurrently programming a set of cells, wherein at least two cells in the set of cells are designated for programming to different threshold voltages corresponding to the at least two specific program states.
A memory device adapted to program a set of multi-level cells, wherein at least two cells in said set are concurrently programmed to different threshold voltages corresponding to at least two specific program states.
A multi-level cell (“MLC”) memory array programming circuit comprising:
- a controller adapted to map a first pair of bits from an input register to a first element of a programming vector associated with at least one specific program state.
A multi-level cell (“MLC”) memory device comprising a non-volatile memory array;
- and a controller adapted to map a first pair of bits from an input register to a first element of a programming vector associated with at least one specific program state.
Dependencies are inferred from the claim text.