Processor architecture
AssigneeMarvell World Trade Ltd.
InventorSehat Sutardja
Life of this patent
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Abstract
A processing system comprises a multiport memory module having N ports, N data communication buses, and N hardware acceleration modules that communicate with a respective one of the N ports on a respective one of the N data communication buses. A first one of the N hardware acceleration modules performs a first processing task on data and transmits the data to the multiport memory module on a first one of the N data communication buses. A second one of the N hardware acceleration modules receives the data from the multiport memory module on a second one of the N data communication buses and performs a second processing task on the data. N is an integer greater than one.
Claims51
A data processing system comprising:
- a multiport memory module having N ports;
- N data communication buses;
- and
- N hardware acceleration modules that communicate with a respective one of the N ports on a respective one of the N data communication buses,
- wherein a first one of the N hardware acceleration modules performs a first processing task on data and transmits the data to the multiport memory module on a first one of the N data communication buses, a second one of the N hardware acceleration modules receives the data from the multiport memory module on a second one of the N data communication buses and performs a second processing task on the data, and wherein N is an integer greater than one.
A data processing system comprising:
- a multiport memory module having N+M ports;
- N+M data communication buses;
- N hardware acceleration modules that communicate with a respective one of the N ports on a respective one of the N data communication buses;
- and
- M programmable sideband processor modules that communicate with a respective one of the M ports on a respective one of the M data communication buses,
- wherein one of the N hardware acceleration modules performs a first processing task on data and transmits the data to the multiport memory module on one of the N data communication buses and one of the M programmable sideband processor modules receives the data from the multiport memory module on one of the M data communication buses and performs a second processing task on the data, and wherein N and M are integers greater than or equal to one.
A data processing system comprising:
- multiport memory means for storing data and having N ports;
- N data communication bus means for transmitting data;
- and
- N hardware acceleration means for communicating with a respective one of the N ports on a respective one of the N data communication bus means,
- wherein a first one of the N hardware acceleration means performs a first processing task on data and transmits the data to the multiport memory means on a first one of the N data communication bus means, a second one of the N hardware acceleration means receives the data from the multiport memory means on a second one of the N data communication buses and performs a second processing task on the data, and wherein N is an integer greater than one.
A data processing method comprising:
- performing a first processing task on data at a first one of N hardware acceleration modules;
- transmitting the data to a respective first one of N ports of a multiport memory module on a respective first one of N data communication buses;
- receiving the data from a respective second one of the N ports of the multiport memory module at a second one of the N hardware acceleration modules on a respective second one of the N data communication buses;
- and
- performing a second processing task on the data at the second one of the N hardware acceleration modules,
- wherein N is an integer greater than one.
Dependencies are inferred from the claim text.