Flash memory circuit for supporting an IDE apparatus
AssigneeSiliconmotion Inc.
InventorsLung-Yi Kuo, Yung-Hao Chang
Life of this patent
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Abstract
The present invention provides a flash memory circuit for accessing an IDE apparatus. This flash memory circuit includes a flash memory controller, a latch circuit and an IDE apparatus. The flash memory controller outputs a latch signal to control the latch circuit to access a special address signal and output a RD/WR signal. The RD/WR signal is used to access data from the IDE apparatus according to the special address signal.
Claims26
A flash memory circuit, wherein said circuit may access an IDE apparatus, comprising:
- a flash memory controller for outputting a latch signal, a writing signal, a reading signal and a data;
- a latch circuit controlled by said latch signal, wherein said latch signal controls said latch circuit to access a special address, and said special address is latched in said latch circuit;
- and
- an IDE apparatus controlled by said writing signal or said reading signal, wherein said writing signal controls said IDE apparatus for writing said data to said IDE apparatus according to said special address, and said reading signal controls said IDE apparatus for reading said data from said IDE apparatus according to said special address.
A method for writing data to an IDE apparatus, wherein a flash memory circuit is used in said method, said flash memory circuit includes a flash memory controller for outputting a latch signal, a writing signal and a reading signal, and a latch circuit coupling with said IDE apparatus, comprising:
- enabling said latch signal to access a special address;
- disabling said latch signal to latch said special address in said latch circuit;
- and
- enabling said writing signal to write said data to said IDE apparatus according to said special address.
A method for reading data from an IDE apparatus, wherein a flash memory circuit is used in said method, said flash memory circuit includes a flash memory controller for outputting a latch signal, a writing signal and a reading signal, and a latch circuit coupling with said IDE apparatus, comprising:
- enabling said latch signal to access a special address;
- disabling said latch signal to latch said special address in said latch circuit;
- and
- enabling said reading signal to read said data from said IDE apparatus according to said special address.
A method for accessing data from an IDE apparatus, wherein a flash memory circuit is used in said method, said flash memory circuit includes a flash memory controller for outputting a latch signal and an accessing signal, a firmware and a latch circuit coupling with said IDE apparatus, comprising:
- setting the clock signal of accessing said IDE apparatus equal to the clock signal of said flash memory by said firmware;
- setting a special access address by said firmware;
- setting a special access count by said firmware;
- enabling said latch signal to access a special address;
- disabling said latch signal to latch said special address in said latch circuit;
- and
- enabling said accessing signal to access said data from said IDE apparatus according to said special address and said special access count.
Dependencies are inferred from the claim text.