DMA transfer and hardware acceleration of PPP frame processing

Abstract

PPP frame encapsulation of IP frames—including FCS calculation, character escaping, and HDLC flag insertion—is performed by hardware acceleration circuits within a DMA module as part of a DMA transfer autonomously of a processor. Software may preprocess the IP packets prior to the hardware-accelerated processing. The hardware acceleration in the DMA module may additionally decapsulate PPP frames—including FCS calculation and comparison for error detection, escaped character recovery, and frame boundary detection—to assist in the formation of IP packets. The hardware-accelerated PPP framing may be particularly useful when a mobile terminal provides internet access, through a wireless communication network over packet data channels, to an attached peripheral device, such as a computer.

Dependencies are inferred from the claim text.