US 2007/0168172 A1Published application

Method to analyze an analog circuit design with a verification program

AssigneeRambus Inc.

InventorsQiang Hong, Kevin Jones, Paul Wong

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Abstract

Data structures and algorithms are provided to automatically generate an analog stimulus to apply to a simulation of the analog DUT. A constraint solver is provided to determine suitable values to use in the stimulus generation. The suitable values are random values within a range of allowed values. For example, a number of different stimuli are generated for successive application to the analog DUT, each with a different magnitude within a range of allowed magnitudes. Data structures and algorithms are provided to monitor analog electrical properties at nodes of the analog DUT. Data structures and algorithms are provided to define constraints on the analog electrical properties and determine whether the constraints were violated. Data structures and algorithms are provided to define simulation coverage conditions in the analog domain and determine whether the defined analog domain coverage conditions have been satisfied.

Claims36

Dependent claims

A method comprising performing a machine-executed operation involving instructions, wherein the machine-executed operation is at least one of:

A) sending the instructions over transmission media;
B) receiving the instructions over transmission media;
C) storing the instructions onto a machine-readable storage medium;
and
D) executing the instructions;
wherein the instructions are instructions which, when executed by one or more processors, cause the one or more processors to perform the steps of:
executing a verification program;
wherein the verification program includes a definition of an analog source;
wherein execution of the verification program generates a stimulus that represents a signal of the analog source;
applying the stimulus to a simulation of at least a portion of an electronic circuit to generate at least one simulation result;
providing the at least one simulation result to the verification program;
and
the verification program performing at least one of:
checking whether the simulation result complies with an expected simulation result;
checking whether an electrical property, based on the simulation result, has a value that violates a constraint on the electrical property specified in the verification program;
and
determining whether the simulation resulted in occurrence of a specified simulation condition specified in the verification program.

14 more elements

A method of simulating a circuit that includes an analog portion, the method including:

executing a verification program;
wherein the verification program includes a definition of a data object;
wherein the definition specifies one or more attributes of the data object;
wherein execution of the verification program causes instantiation of a data structure based on the definition;
wherein the data structure has fields that correspond to the attributes specified by the definition;
during simulation of the circuit, determining a value of an electrical property associated with the analog portion of the circuit;
and
performing at least one of:
a) assigning the value of the electrical property to a field of the data structure;
b) reading a value from a field of the data structure to determine a constraint on the value of the electrical property;
and
generating an indication of a violation if the value of the electrical property associated with the analog portion violates the constraint;
and
c) reading a value from a field of the data structure to determine a set of one or more coverage conditions;
detecting whether the value of the electrical property associated with the analog portion corresponds to a coverage condition within the set of one or more coverage conditions;
and
storing an indication that the coverage condition has been satisfied.

14 more elements

Dependencies are inferred from the claim text.