Device and method for voltage regulator with low standby current

A method for providing a reference voltage for regulating voltage levels, the method comprising:

• receiving a first control signal, the first control signal being associated with a calibration or free from being associated with a calibration,
• processing information associated with the first control signal;
• generating a second control signal based on at least information associated with the first control signal, wherein the second control signal is associated with an active state of a first voltage generation system or an inactive state of the first voltage generation system;
• if the second control signal is associated with the inactive state of the first voltage generation system, deactivating the first voltage generation system and a voltage adjustment system coupled to the first voltage generation system;
• if the second control signal is associated with the active state of the first voltage generation system, performing a calibration process;
• wherein the calibration process includes:
• activating the first voltage generation system and the voltage adjustment system, the voltage adjustment system including a latch system;
• generating a calibration voltage in response to the second control signal;
• processing information associated with the calibration voltage and a reference voltage;
• generating a third control signal based on at least information associated with the calibration voltage and the reference voltage;
• processing information associated with the third control signal;
• generating the reference voltage based on at least information associated with the third control signal;
• generating a fourth control signal associated with a completion of the calibration process;
• deactivating the first voltage generation system and the voltage adjustment system.

An apparatus for providing a reference voltage for regulating voltage levels, the apparatus comprising:

• a first voltage generation system configured to receive a first control signal and output a calibration voltage;
• a voltage adjustment system configured to receive the calibration voltage and a reference voltage and output a second control signal;
• a second voltage generation system configured to receive the second control signal and output the reference voltage;
• wherein the voltage adjustment system includes a latch system configured to receive a third control signal and a fourth control signal and output the first control signal;
• wherein the first control signal is associated with a first state if the third control signal is associated with a calibration and the fourth control signal is free from being associated with a completion of a voltage adjustment by the voltage adjustment system;
• wherein the first control signal is associated with a second state if the third control signal is free from being associated with the calibration or the fourth control signal is associated with the completion of the voltage adjustment by the voltage adjustment system;
• wherein the first state is associated with an active state of the first voltage generation system and the second state is associated with an inactive state of the first voltage generation system;
• wherein the voltage adjustment system is configured to process information associated with the calibration voltage and a reference voltage and determine the second control signal based on at least information associated with the calibration voltage and the reference voltage;
• wherein the second voltage generation system includes:
• a first transistor configured to receive the second control signal;
• a second transistor configured to receive the second control signal;
• a first resistor in parallel with the first transistor;
• a second resistor in parallel with the second transistor;
• a third transistor coupled to the second resistor and the second transistor and configured to generate the reference voltage;
• wherein the second control signal is associated with an “on” state or an “off” state of the first transistor and is associated with an “on” state or an “off” state of the second transistor;
• wherein the first resistor is substantially shorted by the first transistor if the second signal is associated with an active state of the first transistor.