Receiver and electronic device using the same
AssigneePanasonic Corporation
InventorsEiji Okada, Hiroaki Ozeki
Life of this patent
Estimating the term…
Abstract
A receiver and an electronic device are provided that suppress deterioration of the signal waveform of a symbol. The receiver has filter (12) that sends out an output signal having a symbol at an arbitrary time interval; and intermittent operation part (13) that controls filter (12) intermittently at an arbitrary time interval, according to an output signal supplied from filter (12). The makeup prevents deterioration of the signal waveform of a symbol, by setting the timing for switching the signal for controlling the frequency characteristic of filter (12), to an arbitrary period between symbol periods such as a guard interval.
Claims11
A receiver comprising:
- a filter that sends out an output signal having a symbol at an arbitrary time interval;
- and
- an intermittent operation part that controls the filter intermittently at the time interval, according to the output signal supplied from the filter.
A frequency adjusting circuit including:
- a reference filter that sets a phase difference to a reference clock signal;
- a multiplication circuit that multiplies the output signal supplied from the reference filter by the reference clock signal;
- and
- a low-pass filter that is connected to an output of the multiplication circuit, the frequency adjusting circuit providing the reference filter with an output voltage supplied from the low-pass filter, to provide the reference filter with negative feedback, so that a cutoff frequency of the reference filter remains constant, the frequency adjusting circuit comprising:
- a sample hold circuit that holds an output voltage supplied from the low-pass filter for a constant period;
- an analog-to-digital converter that converts an output voltage supplied from the sample hold circuit to digital data;
- a digital-to-analog converter that converts the digital data to an analog adjusted value;
- and
- a register that holds the digital data converted, wherein the frequency adjusting circuit is operated intermittently according to the digital data held by the register.
A frequency adjusting circuit including:
- a reference filter that sets a phase difference to a reference clock signal;
- and
- an XOR circuit that outputs an exclusive OR of the output signal supplied from the reference filter and the reference clock signal;
- and
- a measurement circuit that measures a duty ratio of the output signal supplied from the XOR circuit, the frequency adjusting circuit using the output signal supplied from the measurement circuit for a control signal of the filter, the frequency adjusting circuit comprising a register that holds the output signal supplied from the measurement circuit as digital data, wherein the frequency adjusting circuit is intermittently operated.
Dependencies are inferred from the claim text.