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US 2007/0166997 A1Published application
Semiconductor devices and methods of manufacture thereof
AssigneeInfineon Technologies AG
InventorAndreas Knorr
Life of this patent
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Abstract
Vertically stacked integrated circuits and methods of fabrication thereof are disclosed. Deep vias that provide vertical electrical connection for vertically stacked integrated circuits are formed early in the manufacturing process, before integrated circuits are bonded together to form a three dimensional integrated circuit (3D-IC).
Claims28
A method of fabricating a semiconductor device, the method comprising:
- fabricating a first integrated circuit;
- fabricating a second integrated circuit;
- and
- vertically coupling the second integrated circuit to the first integrated circuit, wherein fabricating the first integrated circuit comprises providing a first workpiece, forming at least one first active area within the first workpiece, and forming at least one deep via within the first workpiece, wherein the at least one deep via provides vertical electrical connection for the first integrated circuit.
1 more element
A method of fabricating a semiconductor device, the method comprising:
- fabricating a first integrated circuit, wherein fabricating the first integrated circuit comprises forming at least one deep via in a first workpiece of the first integrated circuit, before forming an interconnect region of the first integrated circuit;
- and
- coupling a second integrated circuit vertically to the first integrated circuit, wherein the at least one deep via electrically couples a portion of the second integrated circuit to a portion of the first integrated circuit or to an external connection or bond pad of the semiconductor device.
A method of fabricating a three dimensional (3D) integrated circuit (IC), the method comprising:
- providing a first workpiece;
- forming first active areas in the first workpiece;
- forming a plurality of deep vias extending about 5 to 25 μm within the workpiece;
- forming a first interconnect region over the first active areas and the plurality of deep vias;
- providing a second workpiece;
- forming second active areas in the second workpiece;
- forming a second interconnect region over the second active areas;
- and
- vertically coupling the second workpiece to the first workpiece, wherein the plurality of deep vias provide vertical electrical connections for the 3D-IC.
6 more elements
A semiconductor device, comprising:
- a first integrated circuit, the first integrated circuit comprising a workpiece, at least one active area disposed within or over the workpiece, and an interconnect region disposed over the at least one active area;
- a second integrated circuit coupled vertically to the first integrated circuit;
- and
- at least one via extending completely through the first integrated circuit to electrically couple a portion of the first integrated circuit to the second integrated circuit, or to couple a portion of the first integrated circuit to an external connection or bond pad of the first integrated circuit, wherein the at least one via extends through the workpiece and the at least one active area, but not through the interconnect region of the workpiece.
1 more element
Dependencies are inferred from the claim text.