US 2007/0166970 A1 · ALD gate electrode

Abstract

A semiconductor process and apparatus fabricate a metal gate electrode by forming a first conductive layer (22) over a gate dielectric layer (11), forming a transition layer (32) over the first conductive layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition layer is formed, forming a capping conductive layer (44) over the transition layer, and then selectively etching the capping conductive layer, transition layer, and first conductive layer, resulting in the formation of an etched gate stack (52). By forming the transition layer (32) with an atomic layer deposition process in which the amorphizing material (such as silicon, carbon, or nitrogen) is increasingly added, the transition layer (32) is constructed having a lower region (e.g., 31, 33) with a polycrystalline structure and an upper region (e.g., 37, 39) with an amorphous structure that blocks silicon diffusion.

Claims20

Dependent claims

A method for forming a semiconductor structure, comprising:

providing a substrate;
forming a gate dielectric layer over the substrate;
forming a first metal-based layer over the gate dielectric layer;
forming a transition layer over the first metal-based layer using an atomic layer deposition process in which an amorphizing material is increasingly added as the transition layer is formed;
and
depositing a conductive layer on the transition layer.

3 more elements

Dependencies are inferred from the claim text.

ALD gate electrode

Life of this patent

ALD gate electrode

Life of this patent

Abstract

Claims20