US 2007/0166969 A1 · SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Abstract

The invention provides a semiconductor device capable of protecting a low-concentration implantation region from contamination, and a method for manufacturing the same. A photoresist is formed on a TEOS film which is formed all over a substrate, and removed by photo engraving so as to be partially left. This photo resist is of a positive or negative type opposite to a type of a photoresist used for formation of a p-offset region and a diffusion region. Then, the TEOS film is etched back except for a portion just under the photoresist. Thereby, a contamination protective film is formed just under the photoresist, and a side wall is formed on a side face of a gate electrode.

Claims16

Dependent claims

A method for manufacturing a semiconductor device, comprising:

a first region formation step of selectively implanting impurities at a low concentration of not more than 1×1017 cm−3 into a semiconductor substrate to form a first region;
a contamination protective film formation step of forming a contamination protective film on said first region;
and
a second region formation step of selectively implanting impurities at a high concentration of not less than 1×1018 cm−3 into said semiconductor substrate to form a second region at least either prior to or after said first region formation step and said contamination protective film formation step.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

11/623,473Filed 16 Jan 2007

Priority

JP 2006-00947118 Jan 2006

Published

19 Jul 2007

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 84/811
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs: combinations of…
H10D 84/0167
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their channels
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0181
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate insulating layers

Semiconductor device and method for manufacturing the same

Life of this patent

Semiconductor device and method for manufacturing the same

Life of this patent

Abstract

Claims16