Dual isolation structure of semiconductor device and method of forming the same

Abstract

There are provided an isolation structure of a semiconductor device for suppressing the generation of leakage current by preventing two adjacent well regions below an isolation oxide layer from being electrically connected to each other, and a method of forming the same. The dual isolation structure of a semiconductor device is composed of a narrow and deep first isolation layer, and a wide and shallow second isolation layer. For example, the first isolation layer is a thermal oxide layer, and the second isolation layer is a chemical vapor deposition (CVD) layer. A first trench and a second trench are formed between adjacent well regions of the silicon substrate, and are buried with a first isolation layer and a second isolation layer respectively. A width of the first trench is smaller than that of the second trench, and a depth of the first trench is greater than that of the second trench. The second isolation layer is similar to a conventional isolation layer, and since the first isolation layer is formed deeper than the second isolation layer, adjacent well regions can be completely isolated.

Dependencies are inferred from the claim text.