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US 2007/0166946 A1Published application
Method of reducing film stress on overlay mark
AssigneeMacronix International Co., Ltd.
InventorsYu-Lin Yen, Ching-Yu Chang
Life of this patent
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Abstract
An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.
Claims13
A method of fabricating an integrated circuit, comprising:
- providing a first layer having a first overlay mark and a trench;
- forming a second layer having a second layer feature within the trench;
- and
- forming a third layer over the second layer, the third layer being aligned with the first overlay mark and having a third layer feature which is disposed within the trench;
- and
- forming a second overlay mark, the second overlay mark being disposed at a first distance from the first overlay mark and being disposed at a second distance from the trench;
- wherein the second distance changes substantially in response to a profile shift compared to a change in the first distance in response to the profile shift.
4 more elements
Dependencies are inferred from the claim text.