Dual metal silicide scheme using a dual spacer process
AssigneeFreescale Semiconductor, Inc.
InventorsOlubunmi Adetutu, Dharmesh Jawarani, Randy Cotton
Life of this patent
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Abstract
A semiconductor process and apparatus provide a polysilicon structure (10) and source/drain regions (12, 14) formed adjacent thereto in which a dual silicide scheme is used to form first silicide regions in the polysilicon, source and drain regions (30, 32, 34) using a first metal (e.g., cobalt). After forming sidewall spacers (40, 42), a second metal (e.g., nickel ) is used to form second silicide regions in the polysilicon, source and drain regions (60, 62, 64) to reduce encroachment by the second silicide in the source/drain (62, 64) and to reduce resistance in the polysilicon structure caused by agglomeration and voiding from the first silicide (30).
Claims20
A method for forming a semiconductor structure, comprising:
- providing a semiconductor substrate;
- forming a first insulating layer over the semiconductor substrate;
- forming an etched gate stack over the first insulating layer comprising an upper polysilicon layer;
- forming first spacers over the semiconductor substrate on each side of the etched gate stack;
- forming source/drain regions in the semiconductor substrate adjacent to the etched gate stack and first spacers;
- forming a first silicide on any exposed surface of the polysilicon layer and source/drain regions;
- forming second spacers over the semiconductor substrate on each side of the first spacers;
- and
- forming a second silicide on any exposed surface of the polysilicon layer and on any exposed surface of the source/drain regions not covered by the first and second spacers, where the first silicide and the second silicide are different.
A method for forming dual metal silicide regions in a transistor structure having a first polysilicon gate and gate dielectric layer formed over a substrate to define active source/drain regions, comprising:
- forming first silicide regions from a first metal in a first polysilicon gate and in active source/drain regions in the substrate and adjacent to the first polysilicon gate;
- forming spacers over the semiconductor substrate on each side of the first polysilicon gate;
- and
- forming second silicide regions from a second metal in the first polysilicon gate and in any exposed surface of the active source/drain regions not covered by the spacers, where the first and second metals are different.
A method for fabricating silicide regions using two silicide formation processes, comprising:
- forming first silicide regions in a polysilicon gate and active source/drain regions;
- forming sidewall spacers adjacent the polysilicon gate to partially cover the active source/drain regions;
- and
- forming second silicide regions in the polysilicon gate and any exposed surface of the active source/drain regions not covered by the sidewall spacers by using the sidewall spacers to effectively separate the nickel silicide in the active source/drain regions from a channel region below the polysilicon gate, thereby reducing encroachment of the nickel silicide regions.
Dependencies are inferred from the claim text.