Nrom flash memory devices on ultrathin silicon
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
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Abstract
An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.
Claims21
A method for fabricating a memory array comprising a plurality of vertical NROM memory cells, the method comprising:
- forming a first plurality of doped regions in a substrate such that a gap exists between each doped region, the doped regions having a different conductivity type than the substrate;
- forming an oxide pillar over the gap between the doped regions;
- forming an ultra-thin silicon body region extending from each doped region along opposing sidewalls of the oxide pillar;
- forming a second plurality of doped regions in a polysilicon material over the oxide pillar and body regions such that the doped regions over the pillar are electrically coupled and have the same conductivity type as the first plurality of doped regions;
- forming a gate insulator layer over the first plurality of doped regions, the body regions, and the second plurality of doped regions;
- and
- forming a polysilicon gate area over the gate insulator adjacent to each of the body regions.
A method for fabricating a memory array comprising a plurality of vertical NROM memory cells, the method comprising:
- forming a first plurality of doped regions in a substrate, the doped regions having a different conductivity type than the substrate;
- forming an oxide pillar over each doped region such that each end of each doped region extends beyond an adjacent sidewall of the oxide pillar;
- forming an ultra-thin silicon body region by epitaxial regrowth extending from the ends of the doped regions and along opposing sidewalls of the oxide pillar;
- forming a second plurality of doped regions in a polysilicon material over the oxide pillar and body regions such that the doped regions over the pillar are electrically coupled and have the same conductivity type as the first plurality of doped regions;
- forming a gate insulator layer over the first plurality of doped regions, the body regions, and the second plurality of doped regions, the gate insulator layer having a lower layer, adjacent to each end of a doped region of the first plurality of doped regions, that has a thickness greater than remaining portions of the lower layer;
- and
- forming a polysilicon control gate area over the gate insulator adjacent to each of the body regions.
Dependencies are inferred from the claim text.