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US 2007/0166924 A1Published application
Memory cell and method for fabricating a memory device
AssigneeInfineon Technologies AG
InventorsMichael Kund, Thomas Mikolajick, Cay-Uwe Pinnow
Life of this patent
Estimating the term…
Abstract
When fabricating a memory cell with an organic storage layer which stores a digital information item, processing of polycrystalline and monocrystalline semiconductor structures in which high temperatures are employed is concluded prior to application of the organic storage layer.
Claims21
1-20. (canceled)
A method for fabricating a memory device, including semiconductor structures with memory cells in which digital information is stored in a storage layer, the method comprising:
- forming two source/drain regions which are spaced apart from one another by a channel region in a semiconductor substrate;
- producing a gate dielectric on a substrate surface of the semiconductor substrate above the channel region;
- arranging a first gate electrode on the gate dielectric;
- forming the storage layer as an organic layer;
- concluding processing of the semiconductor structures prior to application of the storage layer;
- providing a conductive connection between the storage layer and the first gate electrode;
- and
- arranging an insulator layer above the storage layer and arranging a second gate electrode on the insulator layer.
5 more elements
A memory cell comprising:
- a storage layer that stores a digital information item;
- two source/drain regions that are formed in a semiconductor substrate and that are spaced apart from one another by a channel region;
- a gate dielectric arranged on a substrate surface of the semiconductor substrate above the channel region;
- a first gate electrode arranged on the gate dielectric;
- a conductive connection between the storage layer and the first gate electrode;
- an insulator layer arranged above the storage layer, and a second gate electrode arranged on the insulator layer;
- wherein the storage layer is formed as an organic layer;
- and
- wherein the storage layer is arranged on the first gate electrode or at a distance from the first gate electrode.
6 more elements
A memory device comprising memory cells arranged in rows and semiconductor structures, and which store a digital information item, wherein the memory device includes memory cells comprising:
- a storage layer that stores a digital information item;
- two source/drain regions that are formed in a semiconductor substrate and that are spaced apart from one another by a channel region;
- a gate dielectric arranged on a substrate surface of the semiconductor substrate above the channel region;
- a first gate electrode arranged on the gate dielectric;
- a conductive connection between the storage layer and the first gate electrode;
- an insulator layer arranged above the storage layer, and a second gate electrode arranged on the insulator layer;
- wherein the storage layer is formed as an organic layer;
- and
- wherein the storage layer is arranged on the first gate electrode or at a distance from the first gate electrode.
6 more elements
The memory device of claim 18, wherein:
- to provide source and drain lines, source/drain regions of memory cells which are respectively adjacent in a row are electrically conductively connected to one another by doped regions provided in the semiconductor substrate;
- and
- after a predetermined number of source/drain regions which have been electrically conductively connected to one another by doped regions in the semiconductor substrate, conductive connections to interconnects, which are formed in a metal level and connect the source/drain regions of memory cells, are arranged.
A method for operating a memory device having:
- a storage layer that stores a digital information item;
- two source/drain regions that are formed in a semiconductor substrate and that are spaced apart from one another by a channel region;
- a gate dielectric arranged on a substrate surface of the semiconductor substrate above the channel region;
- a first gate electrode arranged on the gate dielectric;
- a conductive connection between the storage layer and the first gate electrode;
- an insulator layer arranged above the storage layer, and a second gate electrode arranged on the insulator layer;
- wherein the storage layer is formed as an organic layer;
- and
- wherein the storage layer is arranged on the first gate electrode or at a distance from the first gate electrode, the method comprising:
- charging the respective storage layers of selected memory cells by means of an electron tunneling operation through the gate dielectric as a result of voltages being applied to the source/drain regions and the second gate electrode in order to program the memory device;
- discharging the charged storage layers by means of an electron tunneling operation to the channel region or to the source/drain region as a result of an erase voltage, which differs from the voltage applied during programming, being applied to the second gate electrode in order to erase the programming;
- and
- detecting the strength of a drain current as a function of a charge state of the storage layer in order to read the programmed memory device.
10 more elements
Dependencies are inferred from the claim text.