Method of fabrication a double gate field effect transistor device and such a double gate field transistor device

Method of fabricating a double gate field effect transistor device with ultra shallow junctions, comprising the steps of

• providing a substrate having a first carrier layer, a first insulator layer and a semiconductor layer;
• forming a first gate structure on a first surface of the semiconductor layer,
• forming a source and a drain, and a source extension and a drain extension in said semiconductor layer, using an amorphization step,
• preparing a second gate region by a through-the-first-gate-implant process,
• depositing a second insulator layer over the whole of the substrate at the first surface thereof,
• bonding the substrate to a second carrier layer,
• removing the first carrier layer and the first insulator layer,
• wherein subsequently a step of activating at least the source extension and the drain extension is performed with a substantially diffusionless annealing step.