Three-dimensional control-gate architecture for single poly EPROM memory devices fabricated in planar CMOS technology

A three dimensional capacitor structure comprising:

• a semiconductor substrate having one or more transistors fabricated therein, each having a gate with a width greater than or equal to a first line width;
• a shallow trench isolation region located in the semiconductor substrate;
• and
• a patterned polysilicon structure located on the shallow trench isolation region, the patterned polysilicon structure including one or more narrow polysilicon lines, each having a width less than the first line width.

A method comprising:

• forming one or more transistors in a semiconductor substrate, wherein each of the one or more transistors has a gate with a width equal to or greater than a first width;
• forming a capacitor dielectric layer over a first region of the semiconductor substrate;
• forming a patterned polysilicon structure over the capacitor dielectric layer, wherein the patterned polysilicon structure includes one or more narrow polysilicon lines having a width less than the first width;
• and then
• implanting impurities into the first region of the semiconductor substrate using the patterned polysilicon structure as a mask;
• performing a thermal-drive in cycle, wherein the implanted impurities in the first region of the semiconductor diffuse to create a continuous diffusion region under the patterned polysilicon structure.