Semiconductor structures formed by stepperless manufacturing

A non-volatile memory array comprising,

• a plurality of fin blocks arranged in a row on a semiconductor substrate with a plurality of parallel rows and parallel columns defining an X-Y array, each fin block being a non-volatile memory cell,
• a plurality of parallel subsurface bitlines, with one pair of bitlines electrically communicating with all fin blocks in a row, and
• a plurality of parallel supersurface word lines, with one pair of word lines communicating with all fin blocks in a column.

A non-volatile memory array formed by a plurality of fin blocks forming memory cells, each memory cell comprising,

• a first polysilicon floating gate fin insulatively disposed over a semiconductor substrate between subsurface source and drain electrodes with a channel therebetween, the floating gate electrode having an insulative layer surrounding the floating gate and incorporating a tunnel window therein, the tunnel window disposed vertically distal to the substrate,
• a second polysilicon non-floating gate disposed over the floating gate fin in charge transfer communication with the tunnel window and having an insulative layer surrounding said first polysilicon floating gate, and
• a third polysilicon non-floating gate capping the first polysilicon gate and the second polysilicon gate.