Method to control the gate sidewall profile by graded material composition
AssigneeFreescale Semiconductor, Inc.
InventorsMarius Orlowski, Olubunmi Adetutu, Philllip Stout
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Abstract
A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.
Claims22
An integrated circuit transistor comprising:
- a source;
- a drain;
- and
- a gate electrode formed from a conductive layer and having a top region, a bottom region, and first and second opposite vertical side walls, the first and second vertical side walls have a stepped surface such that a first lateral distance between the first and second vertical side walls in the top region is greater than a second lateral distance between the first and second vertical side walls in the bottom region.
An integrated circuit transistor gate electrode comprising:
- a single layer of conductive material, the gate electrode has a top region, a bottom region, and first and second opposite vertical side walls, the first and second vertical side walls have a stepped surface such that a first lateral distance between the first and second vertical side walls in the top region is greater than a second lateral distance between the first and second vertical side walls in the bottom region.
A method of fabricating an integrated circuit transistor, the method comprising:
- fabricating a layer of conductive material;
- performing a first etch of the conductive material to define first and second opposite vertical side walls of a gate electrode;
- and
- performing a second etch of the conductive material to form recess regions in the first and second opposite vertical side walls, the recess regions are located at a bottom of the first and second opposite vertical side walls so that a cross-section of the gate electrode generally approximates a T-shape.
A method of reducing overlap capacitance in an integrated circuit transistor, the method comprising:
- forming a transistor gate electrode from a single layer of conductive material using an etching process, the gate electrode having a T-shaped cross section;
- implanting source and drain regions in a substrate which is located below the gate electrode, a top of the gate electrode defining lateral boundaries of the source and drain regions so that the source and drain regions are not implanted under the gate electrode;
- and
- thermally processing the implanted source and drain regions to laterally diffuse the source and drain regions under the recess regions of the gate electrode.
Dependencies are inferred from the claim text.