US 2007/0166882 A1Published application

Methods for fabricating chip-scale packages having carrier bonds

OwnerTongbi Jiang, Edward Schrockinventors

Life of this patent

Estimating the term…

Loading patent…

Abstract

A chip-scale package and method for making same. A pattern of conductive traces in the form of lead fingers is adhered to the active surface of a semiconductor die, preferably using a dielectric tape. The conductive traces are wire bonded to bond pads of the semiconductor die to establish electrical connections therebetween. Discrete conductive elements are then attached to the conductive traces in a pattern corresponding to a terminal pad pattern on a carrier substrate such as a printed circuit board. The semiconductor die, tape, conductive traces, wire bonds and interior portions of the discrete conductive elements are encapsulated to create a completed chip-scale package having an array of conductive connections protruding through the encapsulant.

Claims9

Dependent claims

A method for fabricating a chip-scale package comprising:

providing a semiconductor die having an active surface having at least one bond pad disposed thereon;
providing at least one conductive trace having an upper surface and a lower surface;
dielectrically attaching at least a portion of the lower surface of said at least one conductive trace to a portion of the active surface of said semiconductor die;
attaching a conductive bond member between said at least one conductive trace and the at least one bond pad disposed on the active surface of said semiconductor die;
attaching at least one carrier bond to a portion of the upper surface of said at least one conductive trace;
and
encapsulating at least portions of said semiconductor die, said at least one conductive trace, said conductive bond and a portion of said at least one carrier bond.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/716,464Filed 9 Mar 2007
Priority: 14 Jan 2000
Published: 19 Jul 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10W 74/129
The semiconductor body being completely enclosed: forming a chip-scale package [CSP]
H10W 72/5445
Dispositions of bond wires: being orthogonal to a side surface of the chip, e.g. parallel arrangements
H10W 72/5522
Comprising metals or metalloids, e.g. silver: comprising gold [Au]
H10W 72/5524
Comprising metals or metalloids, e.g. silver: comprising aluminium [Al]