Method of forming a microelectronic package and microelectronic package formed according to the method

A microelectronic substrate comprising:

• a wafer;
• circuitry disposed within the wafer and including a plurality of bonding pads;
• a plurality of bumping sites disposed on respective ones of the bonding pads, each of the bumping sites comprising:
• a layer comprising a first element disposed on a corresponding one of the bonding pads;
• a layer comprising a second element disposed on the layer comprising the first element;
• a eutectic of the first element and the second element disposed at an interface between the first element and the second element, wherein the eutectic has a melting temperature below a melting temperature of any element other than the eutectic in the at least one joint structure;
• and
• a layer comprising a third element disposed on the layer comprising the second element, wherein the third element is corrosion resistant.

A method of forming a microelectronic package comprising:

• providing a substrate including a plurality of substrate bumping sites;
• providing a die including a plurality of die bumping sites;
• placing the die onto the substrate such that the substrate bumping sites are placed in registration with corresponding ones of the die bumping sites to form a die-substrate combination including pairs of die and substrate bumping sites;
• forming a plurality of joint structures from each pair of die and substrate bumping sites including:
• heating the die-substrate combination within a predetermined heating temperature range to form a bonded die-substrate combination, wherein at least one of the plurality of joint structures comprises a layer including an alloy and intermetallic compound grains dispersed within the alloy, the alloy comprising a mixture of a first element and a second element both chosen such that a eutectic of the first element and second element has a melting temperature below a melting temperature of any element other than the eutectic in the at least one joint structure;
• and each of the intermetallic compound grains comprising a combination of the second element with a third element, wherein the third element is corrosion resistant;
• applying pressure to the die-substrate combination during heating.

A system comprising:

• an electronic assembly including:
• a microelectronic package comprising:
• a substrate;
• a die bonded to the substrate;
• a plurality of joint structures electrically bonding the die to the substrate, at least one of the plurality of joint structures comprising a layer including an alloy and intermetallic compound grains dispersed within the alloy, wherein:
• the alloy comprises a mixture of a first element and a second element both chosen such that a eutectic of the first element and second element has a melting temperature below a melting temperature of any element other than the eutectic in the at least one joint structure;
• and
• each of the intermetallic compound grains comprises a combination of the second element with a third element, wherein the third element is corrosion resistant;
• and
• a main memory coupled to the electronic assembly.