Boxes for Soft Error Rate Calculation
AssigneeHoneywell International Inc.
InventorDavid Fulkerson
Life of this patent
Estimating the term…
Abstract
Memory and logic error rates are predicted by breaking each transistor into theoretical “boxes” with differing sensitivities to ionizing radiation. The box dimensions and critical charge are determined using physics-based equations. The box dimensions and critical charge are used to calculate soft error rate (SER). This box method may be used to calculate SER due to an ion that simultaneously strikes two separate sensitive volumes in order to cause an upset. Additionally, the box method may used to predict upsets that occur when an ion strike pulls a circuit node below ground or above the positive power supply.
Claims22
A method for calculating a soft error rate, comprising in combination:
- identifying at least one transistor in an integrated circuit cell that if impacted by an ion strike can cause an erroneous output of the integrated circuit cell;
- identifying at least one portion of the at least one transistor that is sensitive to the ion strike;
- and
- determining a critical charge and a dimension for the at least one portion.
A method for calculating a soft error rate due to an ion that strikes two transistors to cause an upset, comprising in combination:
- identifying two transistors in an integrated circuit cell that if both are impacted by an ion strike can cause an erroneous output of the integrated circuit cell;
- modeling the two transistors as two boxes each having a dimension;
- and
- calculating a soft error rate due to an ion striking the two boxes as a function of the box dimensions, distance from a center of the first box to the center of the second box, and an integral flux.
A method for calculating a soft error rate to predict upset when an ion strike pulls a circuit node below ground or above a positive power supply, comprising in combination:
- identifying at least one transistor in an integrated circuit cell that if impacted by an ion strike on a body tie region can cause a circuit node to be pulled below ground or above a positive power supply;
- determining a critical charge for an portion of the transistor that includes at least part of a body and part of a drain of the transistor;
- determining an x-dimension for the portion that contains positions in which the critical charge ranges from a minimum critical charge to two times the minimum critical charge;
- characterizing the portion as having a charge equal to an average of the minimum critical charge and two times the minimum critical charge;
- and
- using the critical charge and the dimension to predict a total soft error rate for the integrated circuit cell.
Dependencies are inferred from the claim text.