Integrated data processing circuit with a plurality of programmable processors

A method of manufacturing an integrated circuit, the method comprising:

• selecting dimensions of a two dimensional matrix of processors;
• generating instructions to layout the processors in the matrix with a design computer;
• generating instructions to layout private operand transfer connections between pairs of neighboring processors in the matrix with the design computer;
• automatically generating instructions with the design computer to layout router circuits hierarchically coupled to each other and to the processors in a tree structure, the processors forming leave nodes of the tree structure, the router circuits being arranged to route a message with an address from a root router circuit to an addressed processor selectively via a path through the tree structure, the router circuits each selecting a part of the path under control of the address, the design computer selecting a number of levels of router circuits in the tree structure;
• manufacturing the integrated circuit according to the generated layout.