Clock signal generating circuit
AssigneeElpida Memory, Inc.
InventorYasuhiro Takai
Life of this patent
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Abstract
Each of identically configured logic inverter circuits 10a, 10b, 10c, and 10d comprises a PMOS transistor MP1 (abbreviated as MP1 hereinafter), and NMOS transistors MN1 and MN2 (abbreviated as MN1 and MN2 hereinafter). Gates of MP1 and MN1 are connected to input terminal IN1, gate of MN2 is connected to input terminal IN2, drains of MP1 and MN1 are connected to an output terminal OUT, source of MN1 is connected to the drain of MN2, source of MP1 is connected to a controllable power supply VC, and source of MN2 is grounded. Input terminals IN1 and IN2 of logic inverter circuits 10a, 10b, 10c, and 10d are connected to output terminals OUT of the logic inverter circuits 10b and 10c, 10c and 10d, 10d and 10a, and 10a and 10b respectively. High-speed four-phase clock signals are generated.
Claims10
A clock signal generating circuit comprising:
- first to fourth logic inverter circuits;
- wherein
- said first to fourth logic inverter circuits are respectively connected between first and second power supplies, and respectively comprise first and second input terminals and an output terminal;
- said output terminal is at a second level when said first input terminal is at a first level, with said output terminal being at the first level when said first and second input terminals are at the second level, in each of said logic inverter circuits;
- and
- first input terminals of said first to fourth logic inverter circuits are connected to output terminals of said second, third, fourth, and first logic inverter circuits respectively, and second input terminals of said first to fourth logic inverter circuits are connected to output terminals of said third, fourth, first, and second logic inverter circuits respectively.
A clock signal generating circuit comprising:
- first to fourth two-input NAND circuits connected between first and second power supplies;
- wherein
- one of input terminals of each of said first to fourth two-input NAND circuits is connected to an output terminal of said second, third, fourth, and first two-input NAND circuits respectively, and the other input terminal of each of said first to fourth two-input NAND circuits is connected to an output terminal of said third, fourth, first, and second two-input NAND circuits respectively.
Dependencies are inferred from the claim text.