Repair i/o fuse circuit of semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorSeong Je Park
Life of this patent
Estimating the term…
Abstract
A repair I/O fuse circuit of a semiconductor memory device includes a reduced by as much as half layout area of fuses by replacing what one repair I/O information is represented by existing two I/O fuses with what one repair I/O information is represented by one I/O fuse. The repair I/O fuse circuit includes a plurality of I/O fuse circuits, each having one fuse. A repair signal indicates that there is an address to be replaced. If a chip enable signal is activated, each of the plurality of I/O fuse circuits outputs a repair I/O information signal depending on whether a fuse has been cut.
Claims16
A repair I/O fuse circuit of a semiconductor memory device, comprising:
- a plurality of I/O fuse circuits that output repair I/O information signals depending on whether a fuse has been cut, respectively, in response to a repair signal and a chip enable signal,
- wherein each of the plurality of I/O fuse circuits includes one fuse,
- wherein the repair signal indicates that there is an address to be replaced, and if the chip enable signal is activated, each of the plurality of I/O fuse circuits outputs the repair I/O information signal depending on whether the fuse has been cut.
A repair I/O fuse circuit of a semiconductor memory device, including a plurality of I/O fuse circuits that output repair I/O information signals depending on whether a fuse has been cut, respectively, in response to a repair signal and a chip enable signal, wherein each of the plurality of fuse circuits comprises:
- a feedback unit that combines one of the plurality of repair I/O information signals and the chip enable signal to output a feedback signal;
- a fuse unit that includes one fuse, outputs an output signal depending on whether the fuse has been cut and operates in response to the repair signal and the feedback signal;
- and
- a buffer unit that outputs one of the plurality of repair I/O information signals in response to the output signal of the fuse unit and the repair signal.
Dependencies are inferred from the claim text.