Self timing write architecture for semiconductor memory and method for providing the same

A method for providing self timing write architecture for semiconductor memory device, the method comprising:

• arranging normal memory cells in an array of rows and clusters;
• providing at least one column of dummy cells, each column divided into two blocks of dummy cells for data writing and for providing load respectively;
• generating a dummy word line for enabling dummy cells in response to a write enable signal;
• making a dummy bit line travel a number of rows equal to half a number of rows in said array of normal memory cells and then back;
• writing data in all of said dummy cells for data writing;
• simultaneously accessing a normal memory cell and writing actual data into it;
• signaling completion of write operation when all written dummy cells stabilize;
• and
• starting a recovery operation for a next cycle.

A self timing write architecture for a semiconductor memory device, the self timing write architecture comprising:

• an array of memory cells arranged in rows and columns;
• at least one column of dummy cells, each column divided into a first block of dummy cells to write data and a second block of dummy cells to provide load;
• a write circuitry coupled to the array of memory cells and to said at least one column of dummy cells, said write circuitry being responsive to a write enable signal to cause a dummy bit line to travel a number of rows corresponding to less than a number of all rows in said array of memory cells and then back, said write circuitry further being responsive to the write enable signal to subsequently carry out a write operation in all of said dummy cells of the first block and simultaneously in at least one of said memory cells;
• and
• at least one logic circuit coupled to said at least one column of dummy cells to signal completion of said write operation.

A method for providing a self timing write architecture for semiconductor memory device, the method comprising:

• arranging memory cells in an array of rows and columns;
• providing at least one column of dummy cells, each column divided into two blocks of dummy cells for data writing and for providing load respectively;
• making a dummy bit line travel a number of rows equal to less than a number of rows in said array of memory cells and then back;
• writing data in all of said dummy cells for data writing after said dummy bit line has traveled back, and simultaneously writing data into one of said memory cells in the array;
• and
• signaling completion of said writing in the dummy cells after all written dummy cells stabilize.

A system for providing a self timing write capability for a semiconductor memory device, the system comprising:

• an array of memory cells arranged in rows and columns;
• means for writing data into all cells of a first block of dummy cells and for providing load using a second block of dummy cells, said first and second blocks of dummy cells belonging to at least one column of dummy cells;
• means for making a dummy bit line travel a number of rows equal to less than a number of rows in said array of memory cells and then back;
• wherein said means for writing data in all cells of said first block of dummy cells writes the data after said dummy bit line has traveled back and simultaneously with a writing of data into one of said memory cells in the array;
• and
• means for signaling completion of said writing in the dummy cells after all written dummy cells stabilize.