Nonvolatile semiconductor memory device and programming or erasing method therefor

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in pre-erase programming, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage, and
• in the second charge injection step, charge injection is executed up to a given threshold voltage.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• conditions of the first charge injection and the second charge injection are changed with a production unit.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• conditions of the first charge injection and the second charge injection are changed with a programming or erasing unit.

A programming or erasing method For a nonvolatile semiconductor memory vice having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• conditions of the first charge injection and the second charge injection are set for each production unit in a testing process.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• conditions of the first charge injection and the second charge injection are set for each programming or erasing unit in a testing process.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• conditions of the first charge injection and the second charge injection are set for each programming or erasing unit according to a characteristic in preceding programming or erasing.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• the wait time changes with the length of a left-to-stand time from last data programming until the programming or erasing.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• only the first charge injection step may be executed depending on the length of a left-to-stand time from last data programming until the programming or erasing.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• charge injection conditions in the second charge injection step changes with the length of a left-to-stand time from last data programming until the programming or erasing.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• wait time changes with the degree of the ambient temperature during data programming.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• only the first charge injection step may be executed depending on the degree of the ambient temperature during data programming.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• charge injection conditions in the second charge injection step changes with the degree of the ambient temperature in data programming.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• the wait time changes with the number of times of data programming or erasing.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• only the first charge injection step may be executed depending on the number of times of programming or erasing.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• charge injection conditions in the second charge injection step changes with the number of times of data programming or erasing.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• the wait time changes with a data value immediately before the programming or erasing.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• only the first charge injection step may be executed depending on a data value immediately before the programming or erasing.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• charge injection conditions in the second charge injection step changes with a data value immediately before the programming or erasing.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer and three or more memory cell threshold voltage values, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• charge injection is first executed for memory cells for which a low threshold voltage is set, then charge injection is executed for memory cells for which a higher threshold voltage is set while a wait time after the first charge injection for the memory cells for which a low threshold voltage is set is secured, and thereafter the second charge injection is executed for the memory cells for which a low threshold voltage is set.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer and three or more memory cell threshold voltage values, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• charge injection is first executed for memory cells for which a high threshold voltage is set, then charge injection is executed for memory cells for which a lower threshold voltage is set while a wait time after the first charge injection for the memory cells for which a high threshold voltage is set is secured, and thereafter the second charge injection is executed for the memory cells for which a high threshold voltage is set.

A programming or erasing method for a nonvolatile semiconductor memory device having a top layer and three or more memory cell threshold voltage values, the method comprising, in programming or erasing, a first charge injection step and a second charge injection step executed after the first charge injection step,

• wherein in the first charge injection step, a given wait time is secured after charge injection is executed up to a given threshold voltage,
• in the second charge injection step, charge injection is executed up to a given threshold voltage, and
• whether or not the first charge injection and the second charge injection should be executed in data programming, or both the first charge injection and the second charge injection or only the first charge injection should be executed in pre-erase programming is determined according to the memory cell threshold voltage level.

Electronic equipment comprising:

• a nonvolatile semiconductor memory device having a trap layer, comprising a programming or erasing sequence control circuit for controlling a given wait time after execution of charge injection up to a given memory cell threshold voltage in first charge injection and then controlling second charge injection after the given wait time so that the first charge injection and the second charge injection are executed in programming or erasing;
• and
• a programming or erasing operation selection circuit capable of switching between the first charge injection and the second charge injection after termination of the control of the given wait time in the first charge injection.