Random cache read using a double memory
AssigneeSpansion LLC
InventorsNancy Leong, Sachit Chandra, Hounien Chen
Life of this patent
Estimating the term…
Abstract
A non-volatile memory, such as a Flash memory, is configured to perform a random multi-page read operation. The memory may include a core array of non-volatile memory cells and input lines for receiving an indication of the random multi-page read operation. Further, the memory may include a multi-level volatile memory coupled to the core array that is configured to simultaneously process multiple pages of data from the core array in a pipelined manner. Output lines are coupled to the multi-level volatile memory and output the pages of data from the memory device.
Claims20
A non-volatile memory device configured to perform a random multi-page read operation, the memory device comprising:
- a core array of non-volatile memory cells;
- input lines for receiving an indication of the random multi-page read operation, including an identification of a plurality of pages of data that are to be read from the core array;
- a volatile memory coupled to the core array and configured to simultaneously process multiple ones of the plurality of pages of data from the core array in a pipelined manner;
- and
- output lines coupled to the volatile memory and configured to output the pages of data from the non-volatile memory device.
A memory device comprising:
- a core array of non-volatile memory cells;
- a first output memory coupled to the core array and configured to receive pages of data from the core array;
- and
- a second output memory coupled to the first output memory and configured to receive the pages of data from the first output memory,
- wherein the core array, the first output memory, and the second output memory are configured to perform a page transfer of a first page of data between the core array, the first output memory, and the second output memory in a first pipeline stage while simultaneously performing a page transfer of a second page of data from the second output memory and off of the memory device in a second pipeline stage.
A non-volatile memory device comprising:
- input address lines for receiving addresses that are to be read from the memory device;
- a core array of non-volatile SONOS-type Flash memory cells;
- address decoders coupled to the input address lines and the core array of non-volatile memory cells;
- a first output memory coupled to the core array and configured to receive pages of data from the core array;
- a second output memory coupled to the first output memory and configured to receive the pages of data from the first output memory, the second output memory receiving the pages of data in a pipelined manner relative to the pages of data received by the first output memory;
- I/O buffers coupled to the second output memory;
- and
- output lines coupled to the I/O buffers and configured to output the pages of data from the memory device.
Dependencies are inferred from the claim text.