NAND-type non-volatile memory devices having a stacked structure and associated methods of forming and operating the same

A method of forming a NAND-type nonvolatile memory device, comprising:

• providing a semiconductor substrate;
• forming a first ground selection line and a first string selection line on the substrate in parallel to each other;
• forming a plurality of parallel first word lines on the substrate between the first ground selection line and the first string selection line;
• forming a first impurity-doped region formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line;
• forming a first interlayer dielectric layer on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate;
• patterning the first interlayer dielectric layer to form a hole that exposes the semiconductor substrate;
• forming an epitaxial contact plug that contacts the semiconductor substrate in the hole;
• forming a single crystalline semiconductor layer on the first interlayer dielectric layer that contacts the epitaxial contact plug;
• forming a plurality of parallel second word lines on the single crystalline semiconductor layer;
• forming a second impurity-doped region in the single crystalline semiconductor layer adjacent to the second word lines;
• and
• forming a second interlayer dielectric layer on the plurality of second word lines and the single crystalline semiconductor layer.

A method of operating a NAND-type nonvolatile memory device, the memory device comprising a cell string, the cell string comprising a plurality of cell transistors, the plurality of cell transistors comprising a plurality of parallel sub-strings, a first one of the sub-strings comprising a first plurality of cell transistors connected to first word lines and a second one of the sub-strings comprising a second plurality of cell transistors connected to second word lines, a ground selection transistor is connected to a ground selection line on one side of the plurality of sub-strings, and a string selection transistor is connected to a string selection line on another side of the plurality of sub-strings, the method comprising:

• reading a cell of the first one of the sub-strings by performing the following:
• applying a read voltage to one of the first word lines associated with the cell of the first one of the sub-strings;
• applying a pass voltage to the other ones of the first word lines connected to the first one of the sub-strings;
• and
• applying a voltage of less than zero volts to the word lines connected to the second one of the sub-strings.